KR100235973B1 - Manufacturing method of capacitor in the semiconductor device - Google Patents
Manufacturing method of capacitor in the semiconductor device Download PDFInfo
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- KR100235973B1 KR100235973B1 KR1019970044619A KR19970044619A KR100235973B1 KR 100235973 B1 KR100235973 B1 KR 100235973B1 KR 1019970044619 A KR1019970044619 A KR 1019970044619A KR 19970044619 A KR19970044619 A KR 19970044619A KR 100235973 B1 KR100235973 B1 KR 100235973B1
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- 239000003990 capacitor Substances 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 14
- 238000003860 storage Methods 0.000 claims description 17
- 238000009832 plasma treatment Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 238000005121 nitriding Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 description 78
- 239000007789 gas Substances 0.000 description 10
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 239000010410 layer Substances 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02592—Microstructure amorphous
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- Engineering & Computer Science (AREA)
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Abstract
본 발명은 반도체소자의 캐패시터 형성방법에 관한 것으로, 고유전율을 갖는 Ta2O5막을 유전체막으로 사용하는 캐패시터에서 LPCVD 방법으로 증착된 Ta2O5막의 누설전류 특성을 개선하기 위해서, 증착하고자 하는 전체 Ta2O5막을 LPCVD방법으로 2회에 걸쳐 증착하고, 처음 증착한 Ta2O5막에 특수 처리한 후에 나머지 Ta2O5막을 증착함으로써 캐패시터의 전기적 특성을 개선하여 누설전류가 발생하는 것을 방지하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 기술이다.The present invention relates to a method for forming a capacitor of a semiconductor device, in order to improve the leakage current characteristics of the Ta 2 O 5 film deposited by the LPCVD method in a capacitor using a Ta 2 O 5 film having a high dielectric constant as a dielectric film The entire Ta 2 O 5 film was deposited twice by LPCVD method, and after special treatment on the first deposited Ta 2 O 5 film, the remaining Ta 2 O 5 film was deposited to improve the electrical characteristics of the capacitor to prevent leakage current. It is a technique for preventing and thereby improving the characteristics and reliability of the semiconductor device.
Description
본 발명은 반도체소자의 캐패시터 형성방법에 관한 것으로써, 특히 캐패시터의 유전체로 전기적 특성이 나쁜 LPCVD Ta2O5막을 사용할 경우, 상기 LPCVD Ta2O5막을 두 번에 걸쳐 형성함으로써 캐패시터의 전기적 특성을 개선시키고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device. In particular, when an LPCVD Ta 2 O 5 film having poor electrical properties is used as a dielectric of a capacitor, the LPCVD Ta 2 O 5 film is formed twice to improve the electrical characteristics of the capacitor. The present invention relates to a technology capable of improving and thereby improving the characteristics and reliability of semiconductor devices.
최근 반도체소자이 고집적화 추세에 따라 셀 크기가 감소되어 충분한 정전용량을 갖는 캐패시터를 형성하기가 어려워지고 있다.In recent years, as semiconductor devices have been highly integrated, it has become difficult to form capacitors with sufficient capacitance because the cell size is reduced.
특히, 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자에서는 캐패시터의 정전용량을 증가시키기 위하여 유전상수가 높은 물질을 유전체막으로 사용하거나, 유전체막의 두께를 얇게하거나 또는 전하저장전극의 표면적을 증가시키는 등의 방법이 있다.In particular, in a DRAM device composed of one MOS transistor and a capacitor, a material having a high dielectric constant is used as the dielectric film, a thickness of the dielectric film is increased, or the surface area of the charge storage electrode is increased to increase the capacitance of the capacitor. There is a way.
도시되어 있지는 않지만, 종래기술에 따른 반도체소자의 캐패시터 제조방법을 살펴보면 다음과 같다.Although not shown, looking at the capacitor manufacturing method of the semiconductor device according to the prior art as follows.
먼저, 반도체기판 상에 소자분리 산화막과 게이트산화막을 형성하고, 게이트 전극과 소오스/드레인전극으로 구성되는 모스 전계효과 트랜지스터를 형성한 후, 상기 구조의 전표면에 층간절연막을 형성한다.First, a device isolation oxide film and a gate oxide film are formed on a semiconductor substrate, and a MOS field effect transistor including a gate electrode and a source / drain electrode is formed, and then an interlayer insulating film is formed on the entire surface of the structure.
그 다음 상기 소오스/드레인전극 중 전하저장전극 콘택으로 예정되어 있는 부분 상측의 층간절연막을 제거하여 전하저장전극 콘택홀을 형성하고, 상기 콘택홀을 통하여 소오스/드레인전극과 점촉되는 전하저장전극을 다결정실리콘층 패턴으로 형성한 후, 상기 전하저장전극의 표면에 산화막이나 질화막 또는 산화막-질화막-산화막의 적층구조로된 유전체막을 도포항며, 상기 유전체막상에 전하저장전극을 감싸는 플레이트전극을 형성하여 캐패시터를 완성한다.Next, the interlayer insulating layer on the upper portion of the source / drain electrodes, which is intended as the charge storage electrode contact, is removed to form a charge storage electrode contact hole, and the charge storage electrode contacted with the source / drain electrode is polycrystalline through the contact hole. After forming a silicon layer pattern, a dielectric film having an oxide film, a nitride film, or an oxide film-nitride film-oxide film laminated structure is coated on the surface of the charge storage electrode, and a plate electrode is formed on the dielectric film to surround the charge storage electrode. Complete
상기와 같은 종래기술에 따른 반도체소자의 캐패시터에서 유전체막은 고유전율, 저누설전류밀도, 높은 절연파괴전압 및 상하측 전극과의 안정적인 계면특성 등이 요구되는데, 상기 산화막은 유전상수가 약3.8 정도이고 질화막은 약 7.2 정도로 비교적 작고, 전극으로 사용되는 다결정실리콘층은 비저항이 800 ∼ 1000μΩcm 정도로 비교적 높아 정전용량이 제한된다.In the capacitor of the semiconductor device according to the prior art as described above, the dielectric film is required to have high dielectric constant, low leakage current density, high dielectric breakdown voltage, and stable interfacial characteristics with the upper and lower electrodes, and the oxide film has a dielectric constant of about 3.8. The nitride film is relatively small at about 7.2, and the polysilicon layer used as an electrode has a relatively high resistivity of about 800 to 1000 mu OMEGA cm, thereby limiting capacitance.
상기와 같은 문제점을 해결하기 위하여 산화막-질화막-산화막의 적층구조로된 유전체막 대신에 Ta2O5막과 같은 고유전체막을 사용한다.In order to solve the above problems, a high-k dielectric film such as a Ta 2 O 5 film is used instead of a dielectric film having a stacked structure of an oxide film-nitride film-oxide film.
상기 Ta2O5막은 256M DRAM 이상의 고집적 메모리 소자의 캐패시터의 유전체막으로 사용이 널리 고려되고 있다.The Ta 2 O 5 film is widely considered to be used as a dielectric film of a capacitor of a high density memory device of 256M DRAM or more.
그러나 상기 Ta2O5막을 유전체막으로 사용하는 캐패시터는 상기 Ta2O5막의 증착방법에 따라 캐패시터의 전기적 특성이 크게 변화된다.However, in the capacitor using the Ta 2 O 5 film as the dielectric film, the electrical characteristics of the capacitor change greatly according to the deposition method of the Ta 2 O 5 film.
즉, 플라즈마 화학기상증착(plasma enhanced chemiacl vapor deposition, 이하 PECVD 라 함)방법으로 상기 Ta2O5막을 증착하여 평판 캐패시터를 형성하는 경우, 저압화학기상증착(low pressure chemical vapor deposition, 이하 LPCVD 라 함)방법으로 Ta2O5막을 증착할 때보다 전기적 특성이 우수하다.That is, when the Ta 2 O 5 film is deposited to form a flat plate capacitor by plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) is referred to. The electrical properties are better than that of the Ta 2 O 5 film.
그러나, 실제로 사용되는 캐패시터는 LPCVD Ta2O5막이 많이 사용되지만, PECVD Ta2O5막에 비해서는 누설전류가 높다는 문제점이 있다.However, the capacitor actually used is a lot of LPCVD Ta 2 O 5 film, there is a problem that the leakage current is higher than the PECVD Ta 2 O 5 film.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 캐패시터 형성시 LPCVD Ta2O5막을 두 번에 걸쳐 증착함으로써 캐패시터의 전기적 특성을 개선하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 반도체소자의 캐패시터 형성 방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems of the prior art, by depositing the LPCVD Ta 2 O 5 film twice in the formation of the capacitor to improve the electrical characteristics of the capacitor and thereby to improve the characteristics and reliability of the semiconductor device It is an object of the present invention to provide a method for forming a capacitor.
제1도 및 제2도는 본 발명에 따른 반도체소자의 캐패시터 형성방법을 나타낸 단면도.1 and 2 are cross-sectional views showing a method of forming a capacitor of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체기판 13 : 전하저장전극11
13 : RTN 막 17 : 1차 Ta2O5막13: RTN membrane 17: primary Ta 2 O 5 membrane
19 : 플라즈마처리된 RTN 막 21 : 플라즈마처리된 1차 Ta2O5막19: plasma treated RTN film 21: plasma treated primary Ta 2 O 5 film
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 캐패시터 형성 방법은, 반도체기판 상부에 도프드 다결정실리콘으로 전하저장전극을 형성하는 공정과, 상기 전하저장전극 상부의 자연산화막을 제거하는 공정과, 상기 구조 표면을 질화화하는 공정과, 상기 질화된 표면을 플라즈마 처리하는 공정과, 상기 구조 상부에 1차 Ta2O5막의 일부를 증착하는 공정과, 상기 1차 Ta2O5막을 플라즈마 처리하는 공정과, 상기 구조 상부에 2차 Ta2O5막을 증착하는 공정과, 증착된 상기 1차 및 2차 Ta2O5막을 플라즈마 처리 및 고온 열처리하는 공정과, 상기 구조 상부에 플레이트전극을 형성하는 공정을 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of forming a capacitor of a semiconductor device according to the present invention comprises the steps of forming a charge storage electrode of the doped polycrystalline silicon on the semiconductor substrate, the step of removing the natural oxide film on the charge storage electrode; Nitriding the surface of the structure, plasma treating the nitrided surface, depositing a portion of the primary Ta 2 O 5 film on the structure, and plasma treating the primary Ta 2 O 5 film. step, the structure above the second Ta 2 O 5 and step, a step of the deposition the first and second Ta 2 O 5 film is a plasma treatment and the high temperature heat treatment for depositing a film, the structure in which the upper forming a plate electrode on It characterized by including a process.
이하, 첨부된 도면을 참고로 하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail.
제1도 및 제2도는 본 발명에 따른 반도체소자의 캐패시터 형성방법을 도시한 단면도이다.1 and 2 are cross-sectional views showing a method of forming a capacitor of a semiconductor device according to the present invention.
먼저, 반도체기판(11)에 소자분리 절연막(도시안됨), 게이트산화막(도시안됨), 게인트전극(도시안됨) 및 비트라인(도시안됨) 등의 하부구조물을 형성한다.First, lower structures such as an isolation layer (not shown), a gate oxide layer (not shown), a gain electrode (not shown), and a bit line (not shown) are formed on the
다음, 전체표면에 평탄화막(도시안됨)을 형성한다.Next, a planarization film (not shown) is formed over the entire surface.
그 다음, 도핑되지 않은 산화막으로 층간절연막(도시안됨)을 형성한다.Then, an interlayer insulating film (not shown) is formed of an undoped oxide film.
그리고, 상기 층간절연막은 콘택마스크를 이용하여 콘택부분으로 예정되는 부분에 콘택홀 (도시안됨)을 형성한다.In addition, the interlayer insulating layer forms a contact hole (not shown) in a portion intended to be a contact portion by using a contact mask.
그 다음, 상기 구조의 전표면에 다결정시리콘막(도시안됨)을 화학기상증착방법(Chemical Vapor Deposition, 이하 CVD 라 함)으로 형성한 다음, 상기 콘택홀(도시안됨)내부에만 상기 다결정실리콘막이 남도록 식각하여 상기 콘택홀(도시안됨)을 메우는 콘택플러그(도시안됨)를 형성한다.Then, a polycrystalline silicon film (not shown) is formed on the entire surface of the structure by chemical vapor deposition (CVD), and then the polysilicon film is formed only inside the contact hole (not shown). It is etched so as to form a contact plug (not shown) filling the contact hole (not shown).
그리고, 상기 콘택플러그(도시안됨)와 접촉되는 전하저장전극(13)을 형성한다.In addition, the
여기서, 상기 전하저장전극(13)은 불순물이 도핑된 다결정실리콘으로 형성하며, 전하저장전극(13)의 구조는 실린더형, 핀형 및 다른 구조를 가지는 경우가 있다. 그리고, 상기 전하저장전극(13)의 구조에 반구형 다결정실리콘(hemispherical grained silicate glass, HSG)을 사용하는 경우도 있다.Here, the
그 다음, 전하저장전극(13) 표면에 발생한 자연산화막(도시안됨)을 제거한다.Next, a natural oxide film (not shown) generated on the surface of the
이 때, 상기 자연산화막은 산화막 식각용액인 불산용액, 불산증기 또는 비.오.이(buffer oxide etchant, 이하 BOE 라 함)용액을 사용하여 제거한다.At this time, the natural oxide film is removed using an oxide etching solution, such as hydrofluoric acid solution, hydrofluoric acid vapor or B. oxide (buffer oxide etchant, BOE) solution.
그 후, 상기 전하저장전극(13)인 도프드 다결정실리콘의 전체표면을 질화화시켜 알.티.엔.(rapid thermal nitration, 이하 RTN 라 함)막(15)을 형성한다.Thereafter, the entire surface of the doped polycrystalline silicon, which is the
여기서, 상기 RTV 막(15)은 NH3가스를 이용하여 800 ∼ 900℃ 정도의 온도에서 20 ∼ 120 초 정도 실시한다.Here, the RTV
이어서, 상기 RTN 막(15)의 표면을 N2O 또는 O2가스를 이용하여 플라즈마 처리한다.Subsequently, the surface of the
이것은 상기 RTN 처리된 표면을 SiN에서 SiON 형태로 바꾸어 줌으로써 전기적 특성을 향상시킨다. 이때, 상기 플라즈마처리 조건은 N2O 또는 O2가스에 의한 플라즈마 가스로 130 ∼ 450℃ 온도에서 100 ∼ 300 w 파워(power)로 1 ∼ 20 분간 실시한다.This improves the electrical properties by changing the RTN treated surface from SiN to SiON form. At this time, the plasma treatment conditions are performed for 1 to 20 minutes at a temperature of 130 to 450 w at a temperature of 130 to 450 ° C. with plasma gas by N 2 O or O 2 gas.
다음, 상기 RTN 막(15) 상부에 LPCVD 방법으로 1차Ta2O5막(17)을 일정두께 증착한다.Next, the first Ta 2 O 5
이때, 상기 Ta2O5막(17)은 O2가스와 Ta(OC2H5)5또는 O2가스와 Ta(OCH3)5를 원료로 사용하여 1mTorr ∼ 6 Torr 정도의 압력 및 370 ∼ 450℃ 정도 온도에서 1차로 증착한다.At this time, the Ta 2 O 5 film (17) using O 2 gas and Ta (OC 2 H 5 ) 5 or O 2 gas and Ta (OCH 3 ) 5 as a raw material and a pressure of about 1 mTorr ~ 6 Torr and 370 ~ First deposition at a temperature of about 450 ℃.
여기서, 상기 1차 Ta2O5막(17)은 50 ∼ 70Å 정도 두께로 한다.Here, the primary Ta 2 O 5
또한, 상기 1차 Ta2O5막(17) 비정질이다. (도1)In addition, the primary Ta 2 O 5
그 다음, 상기 1차 Ta2O5막(17)은 플라즈마 처리한다.The primary Ta 2 O 5
이때, 상기 플라즈마처리한 1차 Ta2O5막(19)은 N2O 또는 O2가스에 의한 플라즈마 가스로 130 ∼ 450℃ 정도의 온도에서 처리한다.At this time, the plasma-treated primary Ta 2 O 5 film 19 is treated with a plasma gas by N 2 O or O 2 gas at a temperature of about 130 to 450 ℃.
그리고, 상기 플라즈마 처리공정은 100 ∼ 300 w 정도의 파워로 1 ∼ 20분 간 실시한다.The plasma treatment step is performed for 1 to 20 minutes at a power of about 100 to 300 w.
상기와 같이 N2O 플라즈마 처리를 실시하면, 여기된 산소원자가 Ta2O5막(17) 내의 결함(defect)이 감소하여, 상기 Ta2O5막(17)하부의 플라즈마 처리된 RTN 막(15) 표면을 좀 더 산질화막 형태로 변형시킨다.When subjected to N 2 O plasma treatment as described above, the defect (defect) in the excited oxygen atom is Ta 2 O 5
질화막에 비하여 산질화막은 전기적인 장벽역활을 하므로 누설전류 감소효과를 갖지만, 상기와 N2O 플라즈마처리로 인하여 질화화된 다결정실리콘이 산화가 급격히 일어나지 않으므로 캐패시터의 유효 산화막 두께 증가에 끼치는 영향은 3 Å이하로 미약하다.Compared to the nitride film, the oxynitride film has an effect of reducing leakage current because it acts as an electrical barrier, but since the nitridated polysilicon is not rapidly oxidized due to the N 2 O plasma treatment, the effect of increasing the effective oxide film thickness of the capacitor is 3. Less than Å
또한, 증착하고자 하는 전체 Ta2O5막을 증착한 후, 플라즈마 처리나 UV-O3처리는 표면의 일정깊이의 Ta2O5막에 효과적이지만 전체 Ta2O5막의 처리에는 효과적이지 못하다.In addition, after depositing the entire Ta 2 O 5 film to be deposited, plasma treatment or UV-O 3 treatment is effective for the Ta 2 O 5 film of a certain depth of the surface, but not effective for the treatment of the entire Ta 2 O 5 film.
그리고, 질화화된 면의 산화효과는 더욱 미약하여 일부 Ta2O5막을 형성한 후 처리에 비하여 누설전류 개선 효과는 매우 작다.In addition, the oxidation effect of the nitrided surface is much weaker, and the leakage current improvement effect is very small compared to the treatment after forming some Ta 2 O 5 film.
또한, 750℃ 이상의 산소분위기에서 Ta2O5막을 열처리하는 경우에는 산소가 Ta2O5막으로 확산·투과하여 상기 RTN 막(15)의 표면의 산화는 플라즈마 처리나 UV-O3처리에 비하여 빠르게 일어나고, 국부적으로 산화되는 정도의 차이가 있기 때문에 1차Ta2O5막(17)을 증착한 후, 750℃정도의 고온에서 열처리 하지 않는다.When the Ta 2 O 5 film is heat-treated in an oxygen atmosphere of 750 ° C. or higher, oxygen diffuses and passes through the Ta 2 O 5 film, so that oxidation of the surface of the
한편, 상기 1차Ta2O5막(17)의 두께를 40 ∼ 50Å로 형성하는 경우에는, 상기 Ta2O5막(17)증착전의 플라즈마 처리공정은 생략 가능하다.(도2)On the other hand, in the case where the thickness of the primary Ta 2 O 5
다음, 2차로 LPCVD 방법으로 Ta2O5박막(도시안됨)을 형성한다.Next, a Ta 2 O 5 thin film (not shown) is formed by a second LPCVD method.
이때, 상기 Ta2O5막의 증착조건은 O2가스와 Ta(OC2H5)5또는 O2가스와 Ta(OCH3)5를 원료로 사용하여 1 mTorr ∼ 6 Torr 정도의 압력 및 370 ∼ 450 ℃정도 온도에서 증착한다.At this time, the deposition conditions of the Ta 2 O 5 film is a pressure of about 1 mTorr ~ 6 Torr and 370 ~ using O 2 gas and Ta (OC 2 H 5 ) 5 or O 2 gas and Ta (OCH 3 ) 5 as a raw material Deposit at a temperature of about 450 ℃.
그 다음, 상기 Ta2O5막의 표면을 N2O 플라즈마 처리한다.Then, the surface of the Ta 2 O 5 film is subjected to N 2 O plasma treatment.
그리고, 750 ∼ 820 ℃ 정도의 온도의 O2분위기에서 5 ∼ 30 분 정도 열처리 한다.Then, the heat treatment at 750 to the temperature of the O 2 atmosphere at about 820 ℃ about 5 to 30 minutes.
한편, 상기 열처리공정 대신 RTP방법으로 800 ∼ 900 ℃정도 온도의 O2또는 N2O 분위기에서 70 ∼ 80 초정도 열처리공정을 실시한다.Meanwhile, instead of the heat treatment step, a heat treatment step of about 70 to 80 seconds is performed in an O 2 or N 2 O atmosphere at a temperature of about 800 to 900 ° C. by an RTP method.
그 후, 상기 구조 상부에 TiN 또는 다결정실리콘으로 플레이트전극을 형성한다.Thereafter, a plate electrode is formed on the structure of TiN or polycrystalline silicon.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 캐패시터 형성방법은, 고유전율을 갖는 Ta2O5막을 유전체막으로 사용하는 캐패시터에서 LPCVD 방법으로 증착된 Ta2O5막의 누설전류 특성을 개선하기 위해서, 증착하고자 하는 전체Ta2O5막을 LPCVD 방법으로 2회에 걸쳐 증착하고, 처음 증착한 Ta2O5막에 특수 처리한 후에 나머지 Ta2O5막을 증착함으로써 캐패시터의 전기적 특성을 개선하여 누설전류가 발생하는 것을 방지하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, the method for forming a capacitor of a semiconductor device according to the present invention is to improve the leakage current characteristics of a Ta 2 O 5 film deposited by LPCVD in a capacitor using a Ta 2 O 5 film having a high dielectric constant as a dielectric film. The entire Ta 2 O 5 film to be deposited is deposited twice by LPCVD method, and after special treatment to the first deposited Ta 2 O 5 film, the remaining Ta 2 O 5 film is deposited to improve the electrical characteristics of the capacitor to improve leakage current. Is prevented from occurring and thereby improving the characteristics and reliability of the semiconductor device.
Claims (7)
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970044619A KR100235973B1 (en) | 1997-08-30 | 1997-08-30 | Manufacturing method of capacitor in the semiconductor device |
| GB9812283A GB2326279B (en) | 1997-06-11 | 1998-06-09 | Method of forming a capacitor of a semiconductor device |
| DE19825736A DE19825736C2 (en) | 1997-06-11 | 1998-06-09 | Method of forming a capacitor of a semiconductor device |
| TW087109222A TW396501B (en) | 1997-06-11 | 1998-06-10 | Method of forming a capacitor of a semiconductor device |
| JP17656798A JP3451943B2 (en) | 1997-06-11 | 1998-06-10 | Method for forming capacitor of semiconductor device |
| CN98102096A CN1129171C (en) | 1997-06-11 | 1998-06-11 | Method of forming capacitor of semiconductor device |
| US09/095,696 US5985730A (en) | 1997-06-11 | 1998-06-11 | Method of forming a capacitor of a semiconductor device |
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| KR1019970044619A KR100235973B1 (en) | 1997-08-30 | 1997-08-30 | Manufacturing method of capacitor in the semiconductor device |
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| KR100235973B1 true KR100235973B1 (en) | 1999-12-15 |
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