KR20000039607A - Method for fabricating capacitor of semiconductor device - Google Patents
Method for fabricating capacitor of semiconductor device Download PDFInfo
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- KR20000039607A KR20000039607A KR1019980054997A KR19980054997A KR20000039607A KR 20000039607 A KR20000039607 A KR 20000039607A KR 1019980054997 A KR1019980054997 A KR 1019980054997A KR 19980054997 A KR19980054997 A KR 19980054997A KR 20000039607 A KR20000039607 A KR 20000039607A
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- film
- semiconductor device
- capacitor
- forming
- polysilicon layer
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 239000003990 capacitor Substances 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000010410 layer Substances 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 239000011229 interlayer Substances 0.000 claims abstract description 12
- 238000003860 storage Methods 0.000 claims abstract description 11
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 238000004140 cleaning Methods 0.000 claims description 16
- 239000011259 mixed solution Substances 0.000 claims description 13
- 238000005406 washing Methods 0.000 claims description 11
- 238000005121 nitriding Methods 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000009832 plasma treatment Methods 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000009413 insulation Methods 0.000 abstract 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 abstract 1
- 235000011114 ammonium hydroxide Nutrition 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000000243 solution Substances 0.000 description 12
- 150000004767 nitrides Chemical class 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000001186 cumulative effect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 241000252506 Characiformes Species 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자의 캐패시터 형성방법에 관한 것으로서, 특히 캐패시터의 유전체막으로 Ta2O5막을 사용하는 경우 하부전극인 다결정실리콘층의 표면을 HF/H2O 혼합용액 및 NH4OH/H2O2/H2O 혼합용액으로 순차적으로 세정하여 자연산화막을 소정 두께 형성한 다음, 급속열질화(rapid thermal nitridation, 이하 RTN이라 함)처리하고, Ta2O5막을 형성함으로써 상기 RTN처리공정시 형성되는 질화막과 상기 자연산화막이 반응하여 SiON막을 형성되도록 하여 상기 Ta2O5막과 다결정실리콘층의 계면에서 누설전류의 발생을 적게하여 캐패시터의 전기적 특성을 개선시키고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device. In particular, when a Ta 2 O 5 film is used as a dielectric film of a capacitor, the surface of a polysilicon layer, which is a lower electrode, is mixed with an HF / H 2 O mixed solution and NH 4 OH / H 2. During the RTN treatment process by sequentially cleaning with O 2 / H 2 O mixed solution to form a natural oxide film to a predetermined thickness, then rapid thermal nitridation (RTN), and forming a Ta 2 O 5 film The formed nitride film reacts with the natural oxide film to form a SiON film, thereby reducing the occurrence of leakage current at the interface between the Ta 2 O 5 film and the polysilicon layer, thereby improving the electrical characteristics of the capacitor and thereby the characteristics and reliability of the semiconductor device. It is about how to improve.
최근 반도체소자의 고집적화 추세에 따라 셀 크기가 감소되어 충분한 정전용량을 갖는 캐패시터를 형성하기가 어려워지고 있다.Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size.
특히, 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자에서는 캐패시터의 정전용량을 증가시키기 위하여 유전상수가 높은 물질을 유전체막으로 사용하거나, 유전체막의 두께를 얇게하거나 또는 전하저장전극의 표면적을 증가시키는 등의 방법이 있다.In particular, in a DRAM device composed of one MOS transistor and a capacitor, a material having a high dielectric constant is used as the dielectric film, a thickness of the dielectric film is increased, or the surface area of the charge storage electrode is increased to increase the capacitance of the capacitor. There is a way.
도시되어 있지는 않지만, 종래기술에 따른 반도체소자의 캐패시터 제조방법을 살펴보면 다음과 같다.Although not shown, looking at the capacitor manufacturing method of the semiconductor device according to the prior art as follows.
먼저, 반도체기판 상에 소자분리 산화막과 게이트산화막을 형성하고, 게이트전극과 소오스/드레인전극으로 구성되는 모스 전계효과 트랜지스터 및 비트라인을 형성한 후, 상기 구조의 전표면에 층간절연막을 형성한다.First, a device isolation oxide film and a gate oxide film are formed on a semiconductor substrate, a MOS field effect transistor and a bit line including a gate electrode and a source / drain electrode are formed, and then an interlayer insulating film is formed on the entire surface of the structure.
그 다음 상기 소오스/드레인전극 중 전하저장전극 콘택으로 예정되어 있는 부분 상측의 층간절연막을 제거하여 전하저장전극 콘택홀을 형성하고, 상기 콘택홀을 통하여 소오스/드레인전극과 접촉되는 전하저장전극을 다결정실리콘층 패턴으로 형성한 후, 상기 전하저장전극의 표면에 산화막-질화막-산화막 구조의 유전체막을 형성하고, 상기 유전체막상에 플레이트전극을 형성하여 캐패시터를 완성한다.Next, a charge storage electrode contact hole is formed by removing an interlayer insulating layer on an upper portion of the source / drain electrode, which is intended to be a charge storage electrode contact, and polycrystalline a charge storage electrode contacting the source / drain electrode through the contact hole. After forming the silicon layer pattern, a dielectric film having an oxide film-nitride-oxide film structure is formed on the surface of the charge storage electrode, and a plate electrode is formed on the dielectric film to complete the capacitor.
상기와 같은 종래기술에 따른 반도체소자의 캐패시터에서 유전체막은 고유전율, 저누설전류밀도, 높은 절연파괴전압 및 상하측 전극과의 안정적인 계면특성 등이 요구되는데, 상기 산화막은 유전상수가 약 3.8 정도이고 질화막은 약 7.2 정도로 비교적 작고, 전극으로 사용되는 다결정실리콘층은 비저항이 800 ∼ 1000μΩ㎝ 정도로 비교적 높아 정전용량이 제한된다.In the capacitor of the semiconductor device according to the prior art as described above, the dielectric film requires high dielectric constant, low leakage current density, high dielectric breakdown voltage, and stable interfacial characteristics with the upper and lower electrodes. The oxide film has a dielectric constant of about 3.8. The nitride film is relatively small at about 7.2, and the polysilicon layer used as the electrode has a relatively high resistivity of about 800 to 1000 mu OMEGA cm.
상기와 같은 문제점을 해결하기 위하여 산화막-질화막-산화막의 적층구조로된 유전체막 대신에 Ta2O5막과 같은 고유전체막을 사용한다.In order to solve the above problems, a high-k dielectric film such as a Ta 2 O 5 film is used instead of a dielectric film having a stacked structure of an oxide film-nitride film-oxide film.
상기 Ta2O5막은 256M DRAM 이상의 고집적 메로리 소자의 캐패시터의 유전체막으로 사용이 널리 고려되고 있다.The Ta 2 O 5 film is widely considered to be used as a dielectric film of a capacitor of a high density memory element of 256M DRAM or more.
그러나, 하부전극인 다결정실리콘층이 후속 열공정시 유전체막인 Ta2O5막과 반응하여 SiO2가 형성되는 것을 방지하기 위하여 상기 다결정실리콘층 표면을 800 ∼ 900℃의온도에서 NH3가스를 이용하여 급속질화(rapid thermal nitridation, RTN)처리하여 상기 다결정실리콘층 표면을 질화화시킨다. 한편, 상기 급속질화처리공정을 실시하기 전에 캐패시터의 전기적 특성을 향상시키기 위해 HF/H2O 혼합용액을 사용하여 세정공정을 실시하지만 누설전류를 감소시키는데 한계가 있다.However, in order to prevent the formation of SiO 2 by reacting the polysilicon layer, which is a lower electrode, with the Ta 2 O 5 film, which is a dielectric film in a subsequent thermal process, the surface of the polysilicon layer is used with NH 3 gas at a temperature of 800 to 900 ° C. Rapid thermal nitridation (RTN) treatment to nitride the surface of the polysilicon layer. On the other hand, before the rapid nitriding treatment process to perform the cleaning process using a mixture of HF / H 2 O to improve the electrical characteristics of the capacitor, there is a limit to reduce the leakage current.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 하부전극인 다결정실리콘층 표면을 HF/H2O 혼합용액 및 NH4OH/H2O2/H2O 혼합용액을 사용하여 순차적으로 세정한 다음, 급속질화처리공정을 실시하여 상기 다결정실리콘층과 유전체막인 Ta2O5막이 서로 반응하는 것을 방지하는 베리어막을 형성하여 누설전류 특성을 향상시키는 반도체소자의 캐패시터 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the surface of the polysilicon layer, which is a lower electrode, is sequentially cleaned using a HF / H 2 O mixed solution and a NH 4 OH / H 2 O 2 / H 2 O mixed solution. Then, by forming a barrier film to prevent the polysilicon layer and the Ta 2 O 5 film, which is a dielectric film, from reacting with each other by performing a rapid nitriding process, to provide a method for forming a capacitor of a semiconductor device to improve leakage current characteristics. There is this.
도 1 내지 도 3 은 본 발명에 따른 반도체소자의 캐패시터 형성방법을 나타낸 단면도.1 to 3 are cross-sectional views showing a capacitor forming method of a semiconductor device according to the present invention.
도 4 는 본 발명에 따른 반도체소자의 캐패시터 형성방법에서 세정방법에 따른 누설전류의 특성을 도시한 그래프도.Figure 4 is a graph showing the characteristics of the leakage current according to the cleaning method in the capacitor formation method of the semiconductor device according to the present invention.
도 5 는 본 발명에 따른 반도체소자의 캐패시터 형성방법에서 256M DRAM의 실린더구조를 갖는 캐패시터의 세정방법에 따른 셀 캐패시턴스값과 누설전류의 누적분포율을 도시한 그래프도.FIG. 5 is a graph showing the cumulative distribution rate of cell capacitance and leakage current according to a method of cleaning a capacitor having a cylinder structure of 256M DRAM in the method of forming a capacitor of a semiconductor device according to the present invention. FIG.
도면의 주요부분에 대한 부호 설명Explanation of symbols for the main parts of the drawings
11 : 반도체기판 13 : 층간절연막11 semiconductor substrate 13 interlayer insulating film
15 : 다결정실리콘층 17 : RTN처리된 막15 polycrystalline silicon layer 17 RTN treated film
19 : Ta2O5막 21 : TiN막19: Ta 2 O 5 film 21: TiN film
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 캐패시터 형성방법은,In order to achieve the above object, a method of forming a capacitor of a semiconductor device according to the present invention,
소정의 하부구조물이 형성되어 있는 반도체기판 상부에 저장전극 콘택홀이 구비된 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a storage electrode contact hole on the semiconductor substrate having a predetermined lower structure formed thereon;
상기 층간절연막 상부에 하부전극인 다결정실리콘층을 형성하는 공정과,Forming a polysilicon layer as a lower electrode on the interlayer insulating film;
상기 다결정실리콘층 표면을 HF/H2O 혼합용액으로 세정하는 제1세정공정과,A first cleaning step of washing the surface of the polysilicon layer with a HF / H 2 O mixed solution,
상기 구조를 NH4OH/H2O2/H2O 혼합용액에 담구어 세정하는 제2세정공정과,A second washing step of washing the structure by immersing the structure in a NH 4 OH / H 2 O 2 / H 2 O mixed solution,
상기 다결정실리콘층 상부를 급속질화처리하는 공정과,Rapid nitriding the upper part of the polysilicon layer;
상기 급속질화처리된 다결정실리콘층 상부에 유전막인 Ta2O5막을 형성하는 공정과,Forming a Ta 2 O 5 film, which is a dielectric film, on the rapidly nitrided polysilicon layer;
상기 Ta2O5막을 플라즈마처리 및 고온 열처리하는 공정과,Plasma treatment and high temperature heat treatment of the Ta 2 O 5 film;
상기 Ta2O5막 상부에 상부전극인 TiN막을 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a TiN film as an upper electrode on the Ta 2 O 5 film.
이하, 첨부된 도면을 참고로 하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail.
도 1 내지 도 3 은 본 발명에 따른 반도체소자의 캐패시터 형성방법을 도시한 단면도이다.1 to 3 are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to the present invention.
먼저, 반도체기판(11)에 소자분리 절연막(도시안됨), 게이트산화막(도시안됨), 게이트전극(도시안됨) 및 비트라인(도시안됨) 등의 하부구조물을 형성한다.First, lower structures such as an isolation layer (not shown), a gate oxide layer (not shown), a gate electrode (not shown), and a bit line (not shown) are formed on the semiconductor substrate 11.
다음, 전체표면에 층간절연막(13)을 형성한다.Next, the interlayer insulating film 13 is formed on the entire surface.
그 다음, 저장전극 콘택마스크를 식각마스크로 이용하여 상기 층간절연막(13)을 식각하여 저장전극 콘택홀(도시안됨)을 형성한다.Next, the interlayer insulating layer 13 is etched using the storage electrode contact mask as an etching mask to form a storage electrode contact hole (not shown).
다음, 상기 층간절연막(13) 상부에 상기 저장전극 콘택홀이 매립되도록 다결정실리콘층(15)을 형성한다.Next, a polysilicon layer 15 is formed on the interlayer insulating layer 13 to fill the storage electrode contact hole.
그 다음, 상기 다결정실리콘층(15) 표면을 세정한다.Then, the surface of the polysilicon layer 15 is cleaned.
상기 세정공정은 다음과 같은 조건으로 실시한다.The washing step is carried out under the following conditions.
먼저, 상기 다결정실리콘층(15) 표면을 HF용액을 사용하여 세정한다.First, the surface of the polysilicon layer 15 is cleaned using an HF solution.
상기 HF용액은 HF/H2O 이 1 : 50의 비율로 혼합되어 있고, 이를 사용하여 20 ∼ 40초간 세정공정을 실시한다.In the HF solution, HF / H 2 O is mixed at a ratio of 1:50, and the cleaning step is performed for 20 to 40 seconds using the same.
다음, NH4OH용액을 사용하여 세정공정을 실시한다. 이때, 상기 NH4OH용액은 NH4OH/H2O2/H2O이 1 : 1 : 5의 비율로 혼합되어 있고, 상기 세정공정은 15 ∼ 30℃의 NH4OH/H2O2/H2O 혼합용액에 10 ∼ 20분간 담구어 실시한다.Next, a washing process is performed using NH 4 OH solution. At this time, the NH 4 OH solution is NH 4 OH / H 2 O 2 / H 2 O is mixed in a ratio of 1: 1: 5, the washing process is NH 4 OH / H 2 O 2 of 15 ~ 30 ℃. Dip it in / H 2 O mixed solution for 10 to 20 minutes.
또한, 상기 NH4OH 대신 H2SO4를 포함하는 피라나(piranha)용액을 사용하여 세정공정을 실시하여도, 상기 다결정실리콘층(15) 상부에 자연산화막이 소정 두께 형성되므로 세정효과는 변함없다.In addition, even when the cleaning process is performed using a piranha solution containing H 2 SO 4 instead of NH 4 OH, the cleaning effect is changed because a predetermined thickness is formed on the polysilicon layer 15. none.
그 다음, 상기 다결정실리콘층(15)의 표면을 급속질화처리하여 RTN처리된 막(17)을 형성한다. 상기 급속질화처리공정은 750 ∼ 900℃ 온도에서 NH3가스를 사용하여 실시한다.Next, the surface of the polysilicon layer 15 is rapidly nitrided to form an RTN treated film 17. The rapid nitriding treatment step is carried out using NH 3 gas at a temperature of 750 ~ 900 ℃.
그 다음, 상기 RTN처리된 막(17)의 상부에 Ta2O5막(19)을 저압화학기상증착(low presure chemical vapor deposition, 이하 LPCVD 라 함)방법으로 형성한다. 상기 Ta2O5막(19)은 350 ∼ 450℃의 온도와, 0.1 ∼ 2 torr의 압력으로 유지된 챔버내에서 20 ∼ 50sccm의 O2가스와 350 ∼ 450sccm의 N2가스 분위기에서 0.005 ∼ 2cc의 Ta(C2H5O)5를 원료로 사용하여 증착한다.Next, a Ta 2 O 5 film 19 is formed on the RTN treated film 17 by a low presure chemical vapor deposition (LPCVD) method. The Ta 2 O 5 film 19 is 0.005 to 2 cc in an atmosphere of 20 to 50 sccm O 2 and 350 to 450 sccm N 2 gas in a chamber maintained at a temperature of 350 to 450 ° C. and a pressure of 0.1 to 2 torr. Is deposited using Ta (C 2 H 5 O) 5 as a raw material.
다음, 상기 Ta2O5막(19)은 N2O 플라즈마를 사용하여 300 ∼ 500℃에서 플라즈마 처리한다.Next, the Ta 2 O 5 film 19 is plasma treated at 300 to 500 ° C. using N 2 O plasma.
그 다음, N2O 분위기에서 퍼니스 어닐공정을 750 ∼ 900 ℃ 로 실시한다.In the following, N 2 O atmosphere is performed by the furnace annealing process to 750 ~ 900 ℃.
다음, 상기 Ta2O5막(19) 상부에 상부전극인 TiN막(21)을 화학기상증착(chemical vapor deposition, 이하 CVD라 함)방법으로 200 ∼ 500Å 두께로 형성하되, 300 ∼ 500℃의 온도와 0.1 ∼ 2torr의 압력을 갖는 챔버내에서 TiCl4과 10 ∼ 1000sccm의 NH4를 사용하여 형성한다.Next, a TiN film 21, which is an upper electrode, is formed on the Ta 2 O 5 film 19 to a thickness of 200 to 500 kPa by chemical vapor deposition (hereinafter referred to as CVD). It is formed using TiCl 4 and 10 to 1000 sccm NH 4 in a chamber having a temperature and a pressure of 0.1 to 2 torr.
상기와 같은 방법으로 형성된 캐패시터는 도 4 에 도시된 바와 같은 누설전류 특성을 갖는다.The capacitor formed by the above method has a leakage current characteristic as shown in FIG.
도 4 는 HF, 피라나용액/HF 또는 HF/NH4OH용액에 의한 세정공정에 따른 캐패시터의 전류-전압 특성을 나타낸 그래프도이다. 각각의 세정방법에 따라 유효산화막의 두께가 다르기 때문에 전압의 값은 전기장으로 환산하여 도시되었다.FIG. 4 is a graph showing current-voltage characteristics of a capacitor according to a washing process with HF, Pirana solution / HF or HF / NH 4 OH solution. Since the thickness of the effective oxide film is different according to each cleaning method, the voltage value is shown in terms of an electric field.
도 4 에 도시된 바와 같이 HF 및 피라나용액/HF 를 사용하여 세정한 경우 누설전류의 양이 거의 유사함을 알 수 있고, HF/NH4OH용액를 사용하여 세정한 경우 0 ∼ 12MV/㎝에서 누설전류 특성이 우수한 것을 알 수 있다.As shown in FIG. 4, it can be seen that the amount of leakage current is almost similar when cleaned using HF and pyranha solution / HF, and is 0 to 12 MV / cm when cleaned using HF / NH 4 OH solution. It can be seen that the leakage current characteristics are excellent.
또한, 도 5 는 본 발명에 따른 반도체소자의 캐패시터 형성방법에서 256M DRAM의 실린더구조를 갖는 캐패시터의 세정방법에 따른 셀 캐패시턴스값과 누설전류의 누적분포율을 도시한 그래프도로서, HF를 사용하여 세정공정을 실시한 경우 셀 캐패시턴스(Cs)는 평균값이 23.2(fF/셀)로 HF/NH4OH용액을 사용하여 세정한 경우의 값과 유사하지만, 누설전류 특성은 HF/NH4OH용액으로 세정한 경우가 더 개선된 값은 나타낸다.FIG. 5 is a graph showing the cumulative distribution rate of cell capacitance and leakage current according to the cleaning method of a capacitor having a cylinder structure of 256M DRAM in the method for forming a capacitor of a semiconductor device according to the present invention. When the process is performed, the cell capacitance (Cs) is similar to the value obtained by washing with HF / NH 4 OH solution with an average value of 23.2 (fF / cell), but the leakage current characteristics are washed with HF / NH 4 OH solution. The case indicates a further improved value.
상기와 같은 반도체소자의 캐패시터 형성방법은 반구형실리콘(hemispherical silicon)을 사용하는 실린더형 구조의 캐패시터 형성방법에 적용할 수 있다.The capacitor formation method of the semiconductor device as described above can be applied to a capacitor formation method of a cylindrical structure using hemispherical silicon (hemispherical silicon).
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 캐패시터 형성방법은, Ta2O5막을 유전체막으로 사용하는 캐패시터에서 하부전극으로 사용되는 다결정실리콘층 표면을 HF용액으로 1차 세정한 후, NH4OH/H2O2/H2O 또는 H2SO4/H2O2/H2O혼합용액에 담구어 2차 세정을 실시한 다음, RTN 처리공정을 실시하여 상기 세정공정시 형성되는 산화막과 상기 급속질화처리공정시 형성되는 질화막을 서로 반응시켜 SiON막이 형성되도록 하여 Ta2O5막이 상기 다결정실리콘층과 반응하여 SiO2막이 형성되는 것을 방지함으로써 누설전류 특성을 향상시키고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of forming a capacitor of a semiconductor device according to the present invention, in a capacitor using a Ta 2 O 5 film as a dielectric film, the surface of the polysilicon layer used as the lower electrode is first washed with HF solution, followed by NH 4. After immersion in OH / H 2 O 2 / H 2 O or H 2 SO 4 / H 2 O 2 / H 2 O mixed solution to perform a secondary cleaning, and then performing an RTN treatment process and the oxide film formed during the cleaning process; The nitride film formed during the rapid nitriding treatment process reacts with each other to form a SiON film, thereby preventing the Ta 2 O 5 film from reacting with the polysilicon layer to form a SiO 2 film, thereby improving leakage current characteristics and thereby characteristics of the semiconductor device. And there is an advantage to improve the reliability.
Claims (14)
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100475272B1 (en) * | 2002-06-29 | 2005-03-10 | 주식회사 하이닉스반도체 | Manufacturing Method of Semiconductor Device |
| US7008837B2 (en) | 2003-02-27 | 2006-03-07 | Samsung Electronics, Co., Ltd. | Method of manufacturing capacitor by performing multi-stepped wet treatment on surface of electrode |
| KR100799129B1 (en) * | 2001-12-24 | 2008-01-29 | 주식회사 하이닉스반도체 | Method of manufacturing capacitor for semiconductor memory device |
| KR100818076B1 (en) * | 2001-12-28 | 2008-03-31 | 주식회사 하이닉스반도체 | Method for fabricating capacitor of semiconductor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100799129B1 (en) * | 2001-12-24 | 2008-01-29 | 주식회사 하이닉스반도체 | Method of manufacturing capacitor for semiconductor memory device |
| KR100818076B1 (en) * | 2001-12-28 | 2008-03-31 | 주식회사 하이닉스반도체 | Method for fabricating capacitor of semiconductor device |
| KR100475272B1 (en) * | 2002-06-29 | 2005-03-10 | 주식회사 하이닉스반도체 | Manufacturing Method of Semiconductor Device |
| US7008837B2 (en) | 2003-02-27 | 2006-03-07 | Samsung Electronics, Co., Ltd. | Method of manufacturing capacitor by performing multi-stepped wet treatment on surface of electrode |
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