KR100344250B1 - Method of fabricating capacitor - Google Patents

Abstract

The present invention relates to a method of manufacturing a capacitor, the method comprising providing a conductor layer over a transistor formed on a semiconductor substrate for connecting a source / drain region of a transistor, and forming a semispherical particulate silicon layer on the conductor layer. Implanting ions into the hemispherical particulate silicon layer using an ion implantation method, performing a heat treatment process to convert the ions into a barrier layer on the hemispherical particulate silicon layer, cleaning the surface of the barrier Performing a wet etching process for forming a dielectric on the barrier layer to form an upper electrode on the dielectric layer.

Description

METHODS OF FABRICATING CAPACITOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to the manufacture of semiconductor integrated circuits (ICs), and more particularly to methods of manufacturing capacitors.

Highly Integrated Memory Devices For example, a dynamic LAN access memory (DRAM) with storage capacitors larger than 256 MB can be used to achieve ultra-thin three-dimensional capacitance structures such as stack-type capacitors or trench-type capacitors. It requires the use of a dielectric. These memory devices must have sufficient storage charge to prevent soft errors. Typically, this dielectric layer is made of tantalum oxide (Ta ₂ O ₅ ) by low pressure chemical vapor deposition (LPCVD). The dielectric constant of this tantalum oxide is larger than that of the oxide. The dielectric constant of this tantalum oxide should preferably have a dielectric constant of about 25.

It is well known that the number of defects is inversely proportional to the annealing temperature in the dielectric formation process and the quality of the dielectric layer is directly proportional to the annealing temperature. However, the native oxide layer is formed at the interface between the dielectric layer and the lower electrode during the high temperature annealing process. Therefore, the dielectric constant of the dielectric layer formed in subsequent processing is reduced by the formation of natural oxides, and the capacitance of the capacitor is reduced by the reduced dielectric constant. In contrast, in the low temperature annealing process, the number of defects is not effectively reduced due to the low temperature, and the quality of the dielectric layer is reduced due to this low temperature. Typically, hemispherical grained silicon (HSG) layers are formed to increase the silicon area of the lower electrode, but the HSG layer is sharp. Therefore, the surface of the dielectric layer will be sharp as the dielectric layer is formed in subsequent processing. Therefore, leakage current is generated by the sharp surface of the dielectric layer.

1A to 1D are cross-sectional views illustrating a process of manufacturing a capacitor structure according to a conventional method. Referring to FIG. 1A, a conductor layer 10 is provided. Conductor layer 10 is provided for connecting the source / drain regions of the transistors on a semiconductor substrate structure (not shown in the figure). Other device structures are already formed on the substrate. The substrate is not shown in the drawings in order to simplify and emphasize the features of the conventional method. The conductor layer 10 is formed by, for example, the LPCVD method. For example, the conductor layer 10 is made of doped polysilicon, and furthermore, the conductor layer 10 is used as a lower electrode for a capacitor.

HSG layer 12 is then formed over the surface of conductor layer 10. The HSG layer 12 is formed using, for example, SiH ₄ and Si ₂ H ₆ as reaction gases, and is formed at one temperature between the formation temperatures of amorphous silicon and polysilicon. The annealing process is performed to improve the quality of the HSG layer 12. However, a thin layer of natural oxide 13 is formed on the surface of the HSG gun 12 in the annealing process, and the dielectric constant of the dielectric layer formed in the subsequent process is reduced by the natural oxide 13. Therefore, the native oxide layer 13 is removed during this subsequent process.

Referring to FIG. 1B, the native oxide layer 13 on the surface of the HSG layer 12 is removed by dilute hydrogen fluoride (HF) solution. A thin layer of nitric oxide 14 (SiO _X N _Y ) is formed on the HSG layer 12 by a rapid thermal process (RTP). Since this RTP process is performed with nitrogen gas at a high temperature, a nitrification reaction occurs to form nitric oxide 14. Silicon atoms in the HSG layer 12 react with nitrogen gas by an RTP process. The nitrogen oxide silicon layer 14 is used as a barrier layer to prevent the formation of natural oxides in subsequent heat treatment processes.

Referring to FIG. 1C, a tantalum oxide layer 16 is formed over the nitrogen oxide silicon layer 14 by, for example, LPCVD. The LPCVD method is performed using Ta (OC ₂ H ₅ ) ₅ compound and is performed at about 360-480 ° C. Then, an annealing process is used to increase the density of the tantalum oxide layer 16. This annealing process is carried out with dry oxygen gas or nitrogen gas and is raised to a temperature of about 700-950 ° C. Tantalum oxide layer 16 is used as the dielectric layer for the capacitor. The formation of natural oxides is not effectively inhibited by the nitric oxide silicon layer 14 formed according to conventional methods. In this way, the natural oxide layer 18 is formed at the interface between the tantalum oxide layer 16 and the nitrogen oxide silicon layer 14 during the annealing process. Therefore, the dielectric constant of the dielectric layer and the capacitance of the capacitor are reduced by the natural oxide layer 18.

Moreover, FIG. 1C shows that the surface of HSG layer 12 and the tantalum oxide layer are sharp, as seen in region 19. This is the cause of leakage current in the region 19.

Referring to FIG. 1D, an upper electrode layer 20 made of titanium nitride (TiN) is formed on the surface of tantalum oxide 16 by, for example, sputtering.

Subsequently, a conventional process for completing the formation of the capacitor is performed. Such conventional processes are well known in the art and are therefore omitted here.

The formation of the natural oxide layer 18 is not effectively suppressed by nitric oxide in conventional processes. Therefore, the dielectric constant of the dielectric layer and the capacitance of the capacitor are reduced by the natural oxide layer 18. Annealing temperature is limited by the formation of the native oxide layer 18. Therefore, the quality of the dielectric layer is reduced. Moreover, the leakage current effect of the capacitor is caused by the sharp surface of the dielectric layer.

It is therefore an object of the present invention to provide a method of manufacturing a capacitor for preventing the formation of natural oxides and leakage current of the capacitor to improve the quality of the dielectric layer and to increase the annealing temperature.

1A to 1D are cross-sectional views illustrating a process of manufacturing a capacitor according to a conventional method,

2A-2C are cross-sectional views illustrating the process of a method of manufacturing a capacitor in accordance with one preferred embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

30 conductor layer 32 hemispherical particulate silicon (HSG) layer

33: natural oxide layer 34: barrier layer

36 dielectric layer 38 upper electrode layer

In order to realize the advantages according to the object of the invention, which is embodied as an embodiment and outlined herein, the invention includes a method of manufacturing a capacitor. The method comprises providing a conductor layer to connect a source / drain region of a transistor over a transistor formed on a semiconductor substrate, forming a hemispherical particulate silicon layer over the conductor layer, the hemispherical particulate silicon layer Implanting ions using an ion implantation method, performing a heat treatment process to convert the ions into a barrier layer on the hemispherical particulate silicon layer, performing a wet etching process to clean the surface of the barrier, Forming a dielectric over said barrier layer, and forming a top electrode over said dielectric layer.

A first feature of the invention is that the ions are implanted into the HSG layer and the RTP process is performed to form a barrier on the surface of the HSG layer.

A second feature of the invention is that the natural oxide is prevented by the barrier layer during the annealing process for forming the dielectric layer. Therefore, the annealing temperature can be raised, and the quality of the dielectric layer is improved.

A third feature of the invention is that an HSG layer having a smooth surface can be produced, and the sharp surface of the dielectric layer formed in subsequent processing is prevented. Therefore, the formation of leakage current in the capacitor is prevented, and the quality of the dielectric layer is improved. These objects, features and advantages of the present invention will become apparent from the following detailed description of preferred embodiments of the invention, but are not limited to these embodiments.

2A-2C are cross-sectional views illustrating process steps of a method of manufacturing a capacitor in accordance with one preferred embodiment of the present invention.

Referring to FIG. 2A, a conductor layer 30 is provided, which is provided to connect source / drain regions of a transistor on a semiconductor substrate layer (not shown). Other device structures have already been formed on this substrate. The substrate structure is not shown in the drawings in order to simplify the drawings and to highlight the features of the present invention. For example, a conductor layer 30, such as doped polysilicon, is formed by, for example, LPCVD. Moreover, this conductor layer is used as the lower electrode for the capacitor.

HSG layer 32 is then formed over conductor layer 30. HSG layer 32 is formed using, for example, SiH ₄ and SI ₂ H ₆ as reaction gases, and is performed at a temperature between the formation temperature of amorphous silicon and the formation temperature of polysilicon. The annealing process is performed to improve the quality of the HSG layer 32.

Nitrogen ions are implanted into the HSG layer 32 using the implantation method. The voltage condition of the implantation method is about 10-30 KeV, and the concentration of ions is 5 × 10 ¹⁴ -5 × 10 ¹⁵ / cm 2. A thin barrier layer 34, such as silicon oxide or silicon nitride, is formed on the HSG layer 32 by a high speed heat treatment process (RTP). This RTP process is carried out at high temperature, with nitrogen dioxide (N ₂ O) or oxygen gas, and the nitrification reaction is carried out to form the barrier layer 34, wherein the silicon atoms in the HSG layer 32 are subjected to this RTP process. Reacts with atmospheric gases Barrier layer 34 is used to inhibit the interaction between atmospheric oxygen atoms and silicon atoms in HSG layer 32. Since barrier layer 34 is formed by injecting nitrogen ions directly into HSG layer 32, the mobility of nitrogen atoms is much greater than that of oxygen atoms in the molecular formula of barrier layer 34.

Since the number of defects in the HSG layer 32 is reduced during the RTP process, the quality of the HSG layer 32 is improved. Region 35 is smoothed by the method of the present invention, thereby preventing the generation of leakage currents in the dielectric layer formed during subsequent processing. However, a thin layer of natural oxide 33 is formed on the surface of HSG layer 32 during the RTP process. This natural oxide layer 33 reduces the dielectric constant of the dielectric layer formed during subsequent processing. This natural oxide layer 33 is removed in subsequent processing to prevent this reduction.

Referring to FIG. 2B, the barrier layer 34 is cleaned by wet etching, for example using diluted hydrogen fluoride solution. The native oxide layer 33 on the surface of the barrier layer 34 is removed during the wet etching process.

Then, for example, another RTP process is carried out with nitrogen (N ₂ ) at high temperature to carry out the nitrification reaction to increase the mobility of the nitrogen atoms. This TRP process is performed to enhance the barrier effect of barrier layer 34. According to the present invention, it should be appreciated that after the natural oxide layer 33 is formed, the RTP process may be performed or omitted.

Referring to FIG. 2C, for example, a dielectric layer 36 made of tantalum oxide is deposited by the LPCVD method on the surface of the barrier layer 34. The LPCVD method is performed at about 360-480 ° C. using a [Ta (OC ₂ H ₅ ) ₅ ] compound. An annealing process is then performed to increase the density of the dielectric layer 36. The annealing process is carried out at a temperature of about 700-950 ° C. with dry oxygen or nitrogen gas. According to the method of manufacturing the capacitor of the present invention, the natural oxide is effectively inhibited by the barrier layer 34. Therefore, the annealing temperature rises (above 850 ° C.), the quality of the dielectric layer 36 is improved, and the formation of natural oxide is suppressed.

Finally, the upper electrode layer 38 is formed on the surface of the dielectric layer 36 by, for example, sputtering. Then, the conventional process for completing the formation of the capacitor is performed. This conventional process is well known in the art, so the detailed description is omitted here. Although the invention has been described by way of example in the preferred embodiments, it should be appreciated that the invention is not limited to these embodiments. Hereinafter, another embodiment of the present invention. HSG layer 32 is not formed in this embodiment. After the conductor layer is deposited, the step of forming the HSG layer is not performed. Instead, ions are injected directly into the conductor layer 30. The barrier layer is formed over the surface of the conductor layer 30. The barrier layer is made of silicon oxide or silicon nitride. Subsequently, the same processes as shown in FIGS. 2B-2C are performed to complete the formation of the capacitor.

A first feature of the present invention is that ions are implanted into the HSG layer 32 to form the barrier layer 34 over the surface of the HSG layer 32 and an RTP process is performed. Formation of the natural oxide is prevented by the barrier layer 34 during the formation of the dielectric layer 36.

A second feature of the invention is that the formation of natural oxide is prevented by the barrier layer 34 during the annealing process. Therefore, the annealing temperature can be raised, and the quality of the dielectric layer 36 is improved.

A third feature of the present invention is that an HSG layer 32 having a smooth surface can be produced, eliminating the sharp surface on the dielectric layer 36 formed during subsequent processing. Therefore, the formation of leakage current in the capacitor is prevented, so that the quality of the dielectric layer 36 is improved.

Although the present invention has been illustrated and described in the preferred embodiments, it should be appreciated that the invention is not so limited. On the contrary, the appended claims are broadly construed to cover various modifications and similar arrangements and processes.

Claims (20)

Providing a conductor layer to connect source / drain regions of a transistor formed on the semiconductor substrate; Forming a hemispherical particulate silicon layer over the conductor layer; Implanting ions into the hemisphere particulate silicon layer using an ion implantation method; Performing a heat treatment process to convert the ions on the hemispherical particulate silicon layer into a barrier layer; Performing a wet etch process to clean the surface of the barrier layer; Forming a dielectric over said barrier layer; And Forming a top electrode over said dielectric layer. The method of claim 1, And forming a high speed heat treatment process between performing the wet etch and forming the dielectric layer. The method of claim 2, And the high-speed heat treatment process uses nitrogen gas. The method of claim 1, And the method of forming the conductor layer uses a low pressure chemical vapor deposition method. The method of claim 1, The method of forming the hemispherical particulate silicon layer uses a low pressure chemical vapor deposition method. The method of claim 1, And the ion implantation method has an energy of about 10-30 KeV. The method of claim 1, Wherein the concentration of ions has a concentration of 5 × 10 ¹⁴ -5 × 10 ¹⁵ / cm. The method of claim 1, And the ion comprises nitrogen gas. The method of claim 1, And performing the heat treatment process comprises performing a high speed heat treatment process. The method of claim 9, The method of manufacturing a capacitor, characterized in that for performing the high-speed heat treatment process is performed using nitrogen dioxide gas. The method of claim 9, And performing the high speed heat treatment using oxygen gas. The method of claim 1, And performing the wet process using a dilute floridization solution. The method of claim 1, And the method of forming the dielectric layer is performed using low pressure chemical vapor deposition. The method of claim 1, Forming a dielectric layer using a temperature of about 700-950 ° C. The method of claim 1, Forming the upper electrode using a sputtering method. The method of claim 1, Wherein the dielectric layer comprises tantalum oxide. The method of claim 1, And the upper electrode comprises titanium nitride. The method of claim 1, And wherein said conductor layer comprises doped polysilicon. The method of claim 1, And the barrier layer comprises nitric oxide silicon. The method of claim 1, And the barrier layer comprises silicon nitride.