KR100505413B1 - Method for manufactruing capacitor in semiconductor device - Google Patents
Method for manufactruing capacitor in semiconductor device Download PDFInfo
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- KR100505413B1 KR100505413B1 KR10-2002-0036779A KR20020036779A KR100505413B1 KR 100505413 B1 KR100505413 B1 KR 100505413B1 KR 20020036779 A KR20020036779 A KR 20020036779A KR 100505413 B1 KR100505413 B1 KR 100505413B1
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- tungsten silicide
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- 239000003990 capacitor Substances 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims description 22
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 28
- 238000003860 storage Methods 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000001039 wet etching Methods 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- RKTYLMNFRDHKIL-UHFFFAOYSA-N copper;5,10,15,20-tetraphenylporphyrin-22,24-diide Chemical compound [Cu+2].C1=CC(C(=C2C=CC([N-]2)=C(C=2C=CC=CC=2)C=2C=CC(N=2)=C(C=2C=CC=CC=2)C2=CC=C3[N-]2)C=2C=CC=CC=2)=NC1=C3C1=CC=CC=C1 RKTYLMNFRDHKIL-UHFFFAOYSA-N 0.000 claims description 2
- 239000010408 film Substances 0.000 description 38
- 239000010410 layer Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 229910003071 TaON Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000011164 ossification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 정전 용량을 증대시키면서 안정적인 캐패시터를 형성할 수 있는 반도체 소자의 캐패시터 제조 방법을 개시한 것으로서, 도전플러그를 포함한 반도체 기판을 제공하는 단계와, 기판 상에 도전플러그를 노출시키는 개구부를 가진 캡 옥사이드막을 형성하는 단계와, 개구부를 포함한 캡 옥사이드막을 덮는 텅스텐 실리사이드막을 형성하는 단계와, 텅스텐 실리사이드막에 열처리를 진행하여 표면에 그레인을 성장시키는 단계와, 결과물을 습식 식각하여 스토리지노드 전극을 분리시키는 단계와, 스토리지노드 전극을 덮는 유전막 및 플레이트 전극을 차례로 형성하는 단계를 포함한다.Disclosed is a method of manufacturing a capacitor of a semiconductor device capable of forming a stable capacitor while increasing capacitance, and providing a semiconductor substrate including a conductive plug, and a cap having an opening exposing the conductive plug on the substrate. Forming an oxide film, forming a tungsten silicide film covering a cap oxide film including an opening, heat-treating the tungsten silicide film to grow grain on the surface, and wet etching the resultant to separate the storage node electrode. And sequentially forming a dielectric film and a plate electrode covering the storage node electrode.
Description
본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 특히 정전 용량(capacitance)을 증대시키면서 안정적인 캐패시터를 형성할 수 있는 반도체 소자의 캐패시터의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly to a method of manufacturing a capacitor of a semiconductor device capable of forming a stable capacitor while increasing capacitance.
최근, DRAM을 비롯한 반도체 소자는 농도가 높아짐에 따라 셀 면적은 급격하게 축소되나, 디바이스의 특성을 일정하게 유지하기 위하여 다자인상의 셀 동작에 필요로 하는 일정 용량 이상의 전하 보전 용량의 확보를 위해 공정 개발과 동시에 소자의 신뢰성 확보가 중요하다. Recently, the cell area of semiconductor devices including DRAM decreases rapidly as the concentration increases, but the process is developed to secure a charge holding capacity of a certain capacity required for operation of a multi-phase cell in order to maintain a constant device characteristic. At the same time, it is important to secure the reliability of the device.
여기서, 반도체 메모리 장치의 정전 용량은 메모리 장치의 기억 용량을 결정하는 중요한 변수로서, 상기 정전 용량을 증가시키기 위하여 유전막의 유전율, 캐패시터의 유효면적, 또는 유전막의 두께를 변화시킴으로써 가능하다. Here, the capacitance of the semiconductor memory device is an important parameter for determining the memory capacity of the memory device, which is possible by changing the dielectric constant of the dielectric film, the effective area of the capacitor, or the thickness of the dielectric film in order to increase the capacitance.
이에 따라, 고유전률을 갖는 Ta2O5 또는 TaON 박막을 이용하여 정전 용량을 증가시키거나, 캐패시터의 유효면적을 증가시킨다.Accordingly, the Ta 2 O 5 or TaON thin film having a high dielectric constant is used to increase the capacitance or increase the effective area of the capacitor.
상기 캐패시터의 유효면적의 증가는, 스토리지노드 전극 상부에 소위 HSG(Hemi hemispheric Grain)막을 성장시킴으로서 전극 표면적을 증가시킨다. 상기 HSG막을 성장시켜 정전 용량을 증가시키는 방법은 비정질 실리콘막이 다결정 실리콘막으로 상 변태하는 과정에서 특이한 물리적 현상을 이용한 것으로서, 기판에 비정질 실리콘을 증착한 후 열을 가하여 상기 비정질 실리콘막을 미세한 반구 모양의 그레인(grain)들을 형성하여 스토리지노드 전극의 유효면적을 보다 넓게 형성시킨다.Increasing the effective area of the capacitor increases the electrode surface area by growing a so-called Hemi hemispheric grain (HSG) film on top of the storage node electrode. The method of increasing the capacitance by growing the HSG film uses an unusual physical phenomenon in the process of transforming the amorphous silicon film into the polycrystalline silicon film. Grains are formed to form a larger effective area of the storage node electrode.
그러나, 종래의 방법은 실리콘 재질의 스토리지노드 전극 전면에 HSG막을 형성할 경우, 스토리지노드 전극의 면적 증가에 따른 캐패시터의 정전용량의 증가는 어느 정도 기대할 수 있으나, 후속의 세정 공정에서 상기 HSG막을 포함한 캐패시터의 첨탑 부분이 상대적으로 취약해서 후속 공정을 거치는 동안 그레인이 떨어져서 파티클로 작용하는 문제점이 발생된다.However, in the conventional method, when the HSG film is formed on the entire surface of the storage node electrode made of silicon, the capacitance of the capacitor may increase to some extent due to the increase of the area of the storage node electrode. However, the HSG film may be included in a subsequent cleaning process. The spire portion of the capacitors is relatively fragile, causing the grain to fall and act as particles during the subsequent process.
또한, 실리콘 재질의 스토리지노드 전극의 면저항값이 100Ω/Cm2으로 매우 높기 때문에 캐리어의 이동 시간이 지연되는 문제점이 있었다.In addition, since the sheet resistance of the storage node electrode made of silicon is very high as 100 Ω / Cm 2 , there is a problem that the movement time of the carrier is delayed.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 스토리지노드 전극으로서 표면이 굴곡진 형상을 가진 텅스텐 실리사이드막을 이용함으로써, 캐패시터의 정전 용량을 증대시킬 수 있는 반도체 소자의 캐패시터 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, and by using a tungsten silicide film having a curved surface as a storage node electrode, a method of manufacturing a capacitor of a semiconductor device that can increase the capacitance of the capacitor. The purpose is to provide.
상기와 같은 목적을 달성하기 위하여, 본 발명의 반도체 소자의 캐패시터 제조 방법은, 도전플러그를 포함한 반도체 기판을 제공하는 단계와, 기판 상에 도전플러그를 노출시키는 개구부를 가진 캡 옥사이드막을 형성하는 단계와, 개구부를 포함한 캡 옥사이드막을 덮는 텅스텐 실리사이드막을 형성하는 단계와, 텅스텐 실리사이드막에 열처리를 진행하여 표면에 그레인을 성장시키는 단계와, 결과물을 습식 식각하여 스토리지노드 전극을 분리시키는 단계와, 스토리지노드 전극을 덮는 유전막 및 플레이트 전극을 차례로 형성하는 단계를 포함한 것을 특징으로 한다.In order to achieve the above object, the capacitor manufacturing method of the semiconductor device of the present invention, providing a semiconductor substrate including a conductive plug, forming a cap oxide film having an opening for exposing the conductive plug on the substrate and Forming a tungsten silicide layer covering the cap oxide layer including the opening, heat-treating the tungsten silicide layer to grow grain on the surface, and wet etching the resultant to separate the storage node electrode, and the storage node electrode It characterized in that it comprises the step of sequentially forming a dielectric film and a plate electrode covering.
상기 텅스텐 실리사이드막은 450∼550℃ 온도에서 저압 화학기상증착하며, 500∼1500Å 두께로 형성하는 것이 바람직하다.The tungsten silicide film is a low pressure chemical vapor deposition at a temperature of 450 ~ 550 ℃, preferably formed to a thickness of 500 ~ 15001.
또한, 상기 열처리 단계는, 800℃ 온도에서 진행하는 것이 바람직하다.In addition, the heat treatment step, it is preferable to proceed at 800 ℃ temperature.
(실시예)(Example)
이하, 첨부한 도면을 참조하여, 본 발명의 반도체 소자의 캐패시터 제조방법을 상세히 설명한다.Hereinafter, a capacitor manufacturing method of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 캐패시터 형성 방법을 설명하기 위한 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 캐패시터 형성 방법은, 도 1a에 도시된 바와 같이, 트랜지스터(transistor)(미도시)의 접합영역(소오스 또는 드레인)(2)와 접촉하는 제 1개구부(4)가 형성된 층간 절연막(3)을 구비하는 반도체 기판(1)이 제공된다.In the method for forming a capacitor of a semiconductor device according to the present invention, as shown in FIG. 1A, a first opening 4 is formed in contact with a junction region (source or drain) 2 of a transistor (not shown). There is provided a semiconductor substrate 1 having an interlayer insulating film 3.
이어, 상기 제 1개구부(4)를 포함한 층간절연막(3) 상에 화학기상증착(Chemical Vapor Deposition) 공정에 의해 다결정 실리콘층을 증착 및 에치백하여 제 1개구부(4)를 매립시키는 도전 플러그(5)를 형성한 후, 캐패시터 형성을 위한 캡 옥사이드막(7)을 증착한다. 그런다음, 포토리쏘그라피 (photolithography) 공정에 의해 상기 캡옥사이드막(7)을 식각하여 도전 플러그(4)를 노출시키는 제 2개구부(8)을 형성한다.Subsequently, a conductive plug is deposited and etched back on the interlayer insulating film 3 including the first openings 4 by a chemical vapor deposition process to bury the first openings 4. After forming 5), a cap oxide film 7 for capacitor formation is deposited. Then, the cap oxide film 7 is etched by a photolithography process to form a second opening 8 exposing the conductive plug 4.
그런 다음, 제 2개구부(8)를 포함한 기판 전면에 저압 화학기상증착(Low Pressure Chemical Vapor Deposition) 공정에 의해 500∼1500Å 두께, 바람직하게는 1000Å 두께로 스토리지노드 전극용 텅스텐 실리사이드막(10)을 형성한다. 이때, 저압 화학기상증착 공정은 450∼550℃ 온도에서 진행하며, 상기 온도는 텅스텐 실리사이드막이 결정질 상으로 증착되는 범위이며, 결정질 상은 육방정계(hexagonal)이다. Then, the tungsten silicide film 10 for storage node electrodes is formed on the entire surface of the substrate including the second opening 8 by a low pressure chemical vapor deposition process at a thickness of 500 to 1500 kPa, preferably 1000 kPa. Form. In this case, the low pressure chemical vapor deposition process is carried out at a temperature of 450 ~ 550 ℃, the temperature is a range in which the tungsten silicide film is deposited as a crystalline phase, the crystalline phase is hexagonal (hexagonal).
본 발명에서는 텅스텐 실리사이드막 상을 비정질이 아니라 결정질을 선택하는 이유는 후속 열처리 공정 시 결정질 상이 비정질 상에 비해 그레인 크기는 작으나 빈도수가 증가되기 때문이다. 또한, 본 발명에서 스토리지노드 전극용으로 텅스텐 실리사이드막을 채택하는 이유는 텅스텐 실리사이드막의 비저항값이 10μΩCm 미만으로 종래의 실리콘막에 비해 낮기 때문에 캐리어의 이동시간이 지연되는 것이 억제된다.In the present invention, the reason why the crystalline phase is selected from the tungsten silicide film phase is not amorphous is because the grain size is smaller but the frequency is increased in the subsequent heat treatment process than the amorphous phase. Further, in the present invention, the reason why the tungsten silicide film is adopted for the storage node electrode is that the specific resistance of the tungsten silicide film is less than 10 mu OMEGA Cm, which is lower than that of the conventional silicon film, and thus the delay of the carrier movement time is suppressed.
이 후, 도 1b에 도시된 바와 같이, 상기 텅스텐 실리사이드막에 800℃ 온도에서 빠른 열처리(Rapid Thermal Anneal)(20)를 진행한다. 이때, 상기 빠른 열처리 공정에 의해 텅스텐 실리사이드막은 육방정계에서 정방정계(Tetragonal Phase)로 상전이되며 동시에 그레인이 형성된다. 상기 빠른 열처리 공정(20)을 800℃ 온도에서 진행하는 이유는 웰 내부 도판트의 확산을 최소로 억제할 수있는 영역대이기 때문이다. 도면부호 10a는 빠른 열처리 공정에 의해 표면에 그레인이 성장한 텅스텐 실리사이드막을 도시한 것이다. Thereafter, as illustrated in FIG. 1B, a rapid thermal annealing 20 is performed on the tungsten silicide layer at 800 ° C. At this time, the tungsten silicide film is phase-transformed from a hexagonal system to a tetragonal phase by the rapid heat treatment process, and grains are formed at the same time. The reason why the rapid heat treatment process 20 is performed at 800 ° C. is because it is an area band capable of minimizing diffusion of the dopant in the well. Reference numeral 10a shows a tungsten silicide film having grain grown on its surface by a rapid heat treatment process.
이어, 도 1c에 도시된 바와 같이, 캡 옥사이드막이 노출되는 시점까지 상기 결과의 텅스텐 실리사이드막에 습식 식각 공정을 진행하여 스토리지노드 전극(11)을 분리한다. 이때, 본 발명의 텅스텐 실리사이드막을 결정질상이 아닌 비정질 상을 채택한 경우, 상기 습식 식각 공정에서, 비정질 상은 결정질 상에 비해 그레인 크기가 크기 때문에 그레인 사이의 바닥 부분이 습식액에 의해 식각되면서 그레인과 그레인 사이가 단락되면서 스토리지노드 전극에 골이 형성될 우려가 있다. 따라서, 본 발명에서는 비정질 상이 아닌 결정질 상의 텅스텐 실리사이드막을 채택함으로서, 그레인 간의 단락으로 인한 골 형성 문제를 해결할 수 있다.Subsequently, as shown in FIG. 1C, the storage node electrode 11 is separated by performing a wet etching process on the resultant tungsten silicide layer until the cap oxide layer is exposed. At this time, when the tungsten silicide film of the present invention adopts an amorphous phase rather than a crystalline phase, in the wet etching process, since the amorphous phase has a larger grain size than the crystalline phase, the bottom portion between the grains is etched by the wet liquid and the grains between the grains and the grains. The short circuit may cause a valley to form on the storage node electrode. Therefore, in the present invention, by adopting the crystalline phase of the tungsten silicide film rather than the amorphous phase, it is possible to solve the problem of bone formation due to short circuit between grains.
그런 다음, 도 1d에 도시된 바와 같이, 스토리지노드 전극(11)을 덮는 유전막(12) 및 플레이트 전극용 도전막(13)을 차례로 형성하여 캐패시터 제조를 완료한다. Then, as illustrated in FIG. 1D, the dielectric film 12 covering the storage node electrode 11 and the conductive film 13 for a plate electrode are sequentially formed to complete the capacitor manufacturing.
본 발명에 따르면, 스토리지노드 전극으로서 비저항값이 10Ω/Cm2 미만인 텅스텐 실리사이드막을 채택함으로써, 캐피어 이동 시간이 지연되는 현상이 억제된다. 또한, 상기 텅스텐 실리사이드막에 열처리 및 습식 식각 공정을 진행하여 HSG 구조를 가짐으로써, 캐패시터의 정전 용량을 증대시킬 수 있다.According to the present invention, by adopting a tungsten silicide film having a specific resistance value of less than 10? / Cm 2 as a storage node electrode, the phenomenon of delay in the capacitor movement time is suppressed. In addition, by performing a heat treatment and a wet etching process on the tungsten silicide layer to have an HSG structure, the capacitance of the capacitor may be increased.
이상에서 자세히 설명한 바와같이, 본 발명은 캐패시터의 플레이트 전극으로서 10μΩ/Cm2 미만의 면저항값을 가진 텅스텐 실리사이드막을 채택함으로써, 기존의 실리콘막보다 면저항값이 훨씬 낮기 때문에 캐리어의 이동 시간이 지연되는 현상이 억제된다.As described in detail above, the present invention adopts a tungsten silicide film having a sheet resistance value of less than 10 μΩ / Cm 2 as a plate electrode of a capacitor, thereby delaying carrier movement time because the sheet resistance value is much lower than that of a conventional silicon film. This is suppressed.
또한, 본 발명에서는 HSG 구조의 텅스텐 실리사이드막이 기존의 실리콘막보다 그레인 밀도가 크기 때문에 정전 용량을 증가시킬 뿐만 아니라, 후속의 세정 공정에서 캐패시터의 첨탑 부분의 그레인이 떨어질 우려가 없다.In addition, in the present invention, since the tungsten silicide film having the HSG structure has a larger grain density than the conventional silicon film, not only does the capacitance increase, but there is no fear that the grain of the spire portion of the capacitor falls in the subsequent cleaning process.
한편, 상기 텅스텐 실리사이드막은 게이트 전극에도 적용되기 때문에 추가적인 장비 투자없이 캐패시터의 스토리지노드 전극을 형성할 수 있다. Meanwhile, since the tungsten silicide layer is also applied to the gate electrode, the storage node electrode of the capacitor can be formed without additional equipment investment.
기타, 본 발명은 그 요지를 벗어나지 않는 범위내에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
도 1a 내지 도 1d는 본 발명의 반도체 소자의 캐패시터 제조방법을 설명하기 위한 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device of the present invention.
* 도면의 주요 부분에 대한 부호 설명 *Explanation of symbols on the main parts of the drawings
1. 반도체 기판 2. 접합영역1. Semiconductor substrate 2. Junction area
3. 층간절연막 4,8 개구부3. Interlayer insulating film 4,8 opening
5. 도전 플러그 7. 캡 옥사이드막 5. Conductive plug 7. Cap oxide film
10, 10a. 텅스텐 실리사이드막 11. 스토리지노드 전극10, 10a. Tungsten Silicide Film 11.Storage Node Electrode
12, 유전막 13. 플레이트 전극용 도전막12, Dielectric Film 13. Conductive Film for Plate Electrode
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| JPH08306882A (en) * | 1995-05-11 | 1996-11-22 | Nec Corp | Semiconductor device and fabrication method thereof |
| KR970030815A (en) * | 1995-11-01 | 1997-06-26 | 김주용 | Capacitor Manufacturing Method of Semiconductor Device |
| KR980006315A (en) * | 1996-06-21 | 1998-03-30 | 김주용 | Method for forming charge storage electrode of semiconductor device |
| US6004857A (en) * | 1998-09-17 | 1999-12-21 | Taiwan Semiconductor Manufacturing Company | Method to increase DRAM capacitor via rough surface storage node plate |
| US6087240A (en) * | 1995-07-17 | 2000-07-11 | Micron Technology, Inc. | Method of forming rough polysilicon surfaces suitable for capacitor construction |
| KR20010001594A (en) * | 1999-06-07 | 2001-01-05 | 김영환 | Method for forming capacitor having tungsten silicide bottom electrode |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH08306882A (en) * | 1995-05-11 | 1996-11-22 | Nec Corp | Semiconductor device and fabrication method thereof |
| US6087240A (en) * | 1995-07-17 | 2000-07-11 | Micron Technology, Inc. | Method of forming rough polysilicon surfaces suitable for capacitor construction |
| KR970030815A (en) * | 1995-11-01 | 1997-06-26 | 김주용 | Capacitor Manufacturing Method of Semiconductor Device |
| KR100200298B1 (en) * | 1995-11-01 | 1999-06-15 | 김영환 | Capacitor device fabrication method of semiconductor |
| KR980006315A (en) * | 1996-06-21 | 1998-03-30 | 김주용 | Method for forming charge storage electrode of semiconductor device |
| US6004857A (en) * | 1998-09-17 | 1999-12-21 | Taiwan Semiconductor Manufacturing Company | Method to increase DRAM capacitor via rough surface storage node plate |
| KR20010001594A (en) * | 1999-06-07 | 2001-01-05 | 김영환 | Method for forming capacitor having tungsten silicide bottom electrode |
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