KR960019572A - Semiconductor Integrated Circuit Dielectric Film Formation Method - Google Patents

Semiconductor Integrated Circuit Dielectric Film Formation Method Download PDF

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Publication number
KR960019572A
KR960019572A KR1019940029783A KR19940029783A KR960019572A KR 960019572 A KR960019572 A KR 960019572A KR 1019940029783 A KR1019940029783 A KR 1019940029783A KR 19940029783 A KR19940029783 A KR 19940029783A KR 960019572 A KR960019572 A KR 960019572A
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KR
South Korea
Prior art keywords
forming
reaction layer
nitride film
silicon nitride
layer
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KR1019940029783A
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Korean (ko)
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KR0151619B1 (en
Inventor
전영권
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문정환
금성일렉트론 주식회사
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Priority to KR1019940029783A priority Critical patent/KR0151619B1/en
Publication of KR960019572A publication Critical patent/KR960019572A/en
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Publication of KR0151619B1 publication Critical patent/KR0151619B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 반도체집적회로의 유전체막 형성방법으로써, 1) 실리콘 기판에 질소를 주입하여 기판내에 반응층을 형성하는 단계와, 2) 그 위에 저압화학기상증착법으로 실리콘질화막층을 형성하는 단계와, 3) 상기 2)단계에서 형성된 실리콘질화막 상에 탑 옥시데이션시키는 단계를 포함하여 이루어진다.The present invention provides a method for forming a dielectric film of a semiconductor integrated circuit, comprising the steps of: 1) injecting nitrogen into a silicon substrate to form a reaction layer in the substrate, and 2) forming a silicon nitride film layer thereon by low pressure chemical vapor deposition; 3) top oxidizing the silicon nitride film formed in step 2).

또한, 반도체장치에서는 캐패시터 형성방법은 1) 실리콘 기판위에 축전전극을 형성하는 단계와, 2) 상기 축전전극에 질소를 주입하여 반응층을 형성하는 단계와, 3) 그 위에 저압화학기상증착법으로 실리콘질화막층을 형성하는 단계와, 4) 상기 3)단계에서 형성된 실리콘질화막층 상에 탑 옥시데이션시키는 단계와, 5) 그 위에 대향전극을 형성하는 단계를 포함하여 이루어진다.In the semiconductor device, a capacitor forming method includes the steps of 1) forming a storage electrode on a silicon substrate, 2) forming a reaction layer by injecting nitrogen into the storage electrode, and 3) using a low pressure chemical vapor deposition method thereon. Forming a nitride film layer, 4) top oxidizing the silicon nitride film layer formed in step 3), and 5) forming a counter electrode thereon.

Description

반도체 집적회로 유전체막 형성방법Semiconductor Integrated Circuit Dielectric Film Formation Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 반도체집적회로 유전체막 형성방법을 도시한 도면.2 is a diagram showing a method for forming a semiconductor integrated circuit dielectric film of the present invention.

Claims (7)

반도체집적회로의 유전체막 형성방법에 있어서, 1) 실리콘 기판에 질소를 주입하여 기판내에 반응층을 형성하는 단계와, 2) 그 위에 저압화학기상증착법으로 실리콘질화막층을 형성하는 단계와, 3) 상기 2)단계에서 형성된 실리콘질화막 상에 탑 옥시데이션시키는 단계를 포함하여 이루어진 반도체 집적회로의 유전체막층 형성방법.A method of forming a dielectric film of a semiconductor integrated circuit, comprising the steps of: 1) injecting nitrogen into a silicon substrate to form a reaction layer in the substrate, and 2) forming a silicon nitride film layer thereon by low pressure chemical vapor deposition; A method of forming a dielectric film layer of a semiconductor integrated circuit comprising the step of top oxidizing on the silicon nitride film formed in step 2). 제1항에 있어서, 상기 1)단계에서 반응층의 형성은 질소를 포함하는 플라즈마에 노출시켜 반응층을 형성하는 것을 특징으로 하는 반도체 집적회로의 유전체막층 형성방법.The method of claim 1, wherein the forming of the reaction layer in step 1) comprises exposing a plasma containing nitrogen to form a reaction layer. 제1항에 있어서, 상기 1)단계에서 반응층의 형성은 질소이온을 주입하고 열처리 공정을 실시하여 반응층을 형성하는 것을 특징으로 하는 반도체 집적회로의 유전체막층 형성방법.The method of claim 1, wherein the forming of the reaction layer in step 1) comprises injecting nitrogen ions and performing a heat treatment to form a reaction layer. 반도체장치에서의 캐패시터 형성방법에 있어서, 1) 실리콘 기판위에 축전전극을 형성하는 단계와, 2) 상기 축전전극에 질소를 주입하여 반응층을 형성하는 단계와, 3) 그 위에 저압화학기상증착법으로 실리콘질화막층을 형성하는 단계와, 4) 상기 3)단계에서 형성된 실리콘질화막층 상에 탑 옥시데이션시키는 단계와, 5) 그 위에 대향전극을 형성하는 단계를 포함하여 이루어진 다이나믹 램 캐패시터 형성방법.A method of forming a capacitor in a semiconductor device, comprising: 1) forming a storage electrode on a silicon substrate, 2) forming a reaction layer by injecting nitrogen into the storage electrode, and 3) using a low pressure chemical vapor deposition method thereon. Forming a silicon nitride film layer, 4) top oxidizing the silicon nitride film layer formed in step 3), and 5) forming a counter electrode thereon. 제4항에 있어서, 상기 축전전극 및 대향전극은 다결정 실리콘인 것을 특징으로 하는 다이나믹 램 캐패시터 형성방법.5. The method of claim 4, wherein the storage electrode and the counter electrode are polycrystalline silicon. 제4항에 있어서, 상기 2)단계에서 반응층의 형성은 질소를 포함하는 플라즈마를 노출시켜 반응층을 형성하는 것을 특징으로 하는 다이나믹 램 캐패시터 형성방법.The method of claim 4, wherein the forming of the reaction layer in step 2) is characterized in that to form a reaction layer by exposing a plasma containing nitrogen. 제4항에 있어서, 상기 2)단계에서 반응층의 형성은 질소이온을 주입하고 열처리공정을 실시하여 반응층을 형성하는 것을 특징으로 하는 다이나믹 램 캐패시터 형성방법.5. The method of claim 4, wherein the forming of the reaction layer in step 2) comprises injecting nitrogen ions and performing a heat treatment to form the reaction layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940029783A 1994-11-14 1994-11-14 Forming method of dielectric film in the semiconductor device KR0151619B1 (en)

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Application Number Priority Date Filing Date Title
KR1019940029783A KR0151619B1 (en) 1994-11-14 1994-11-14 Forming method of dielectric film in the semiconductor device

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KR960019572A true KR960019572A (en) 1996-06-17
KR0151619B1 KR0151619B1 (en) 1998-12-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100815963B1 (en) * 2006-10-11 2008-03-21 동부일렉트로닉스 주식회사 Manufacturing method of capacitor of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100815963B1 (en) * 2006-10-11 2008-03-21 동부일렉트로닉스 주식회사 Manufacturing method of capacitor of semiconductor device

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