KR970018760A - 질화규소 세라믹회로기판 및 이것을 이용한 반도체장치 - Google Patents

질화규소 세라믹회로기판 및 이것을 이용한 반도체장치 Download PDF

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Publication number
KR970018760A
KR970018760A KR1019960042429A KR19960042429A KR970018760A KR 970018760 A KR970018760 A KR 970018760A KR 1019960042429 A KR1019960042429 A KR 1019960042429A KR 19960042429 A KR19960042429 A KR 19960042429A KR 970018760 A KR970018760 A KR 970018760A
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South Korea
Prior art keywords
circuit board
glass layer
silicon nitride
nitride ceramic
glass
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KR1019960042429A
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KR100244823B1 (ko
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미츠오 가소리
아키히로 히로구치
히로야스 스미노
후미오 우에노
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니시무로 타이조
가부시키가이샤 도시바
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Publication of KR970018760A publication Critical patent/KR970018760A/ko
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Publication of KR100244823B1 publication Critical patent/KR100244823B1/ko

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    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
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    • C04B2237/86—Joining of two substrates at their largest surfaces, one surface being complete joined and covered, the other surface not, e.g. a small plate joined at it's largest surface on top of a larger plate
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/732—Location after the connecting process
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Abstract

본 발명의 반도체장치는 열전도율이 실온하에서 80W/mk 이상인 질화규소 세라믹판(1)을 구비하고, 상기 질화규소 세라믹판에 유리층을 매개로 금속판(2)이 접합되어 있고, 상기 반도체장치에는 회로기판이 탑재되어 있다.

Description

질화규소 세라믹회로기판 및 이것을 이용한 반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
도 1은 질화규소 세라믹 회로기판의 도면.

Claims (16)

  1. 열전도율이 실온하에서 80W/mk 이상인 질화규소 세라믹판을 구비하고, 상기 질화규소 세라믹판에 유리층을 매개로 금속판이 접합되어 있는 것을 특징으로 하는 회로기판.
  2. 제1항에 있어서, 상기 유리층은 산화물유리층인 것을 특징으로 하는 회로기판.
  3. 제1항에 있어서, 상기 유리층은 질소량이 0.05~7중량%인 질화물유리층인 것을 특징으로 하는 회로기판.
  4. 제1항에 있어서, 상기 유리층은 결정화 유리층인 것을 특징으로 하는 회로기판.
  5. 제1항에 있어서, 상기 유리층은 산화물확산에서 알카리금속을 0.01~2중량%를 함유한 것을 특징으로 하는 회로기판.
  6. 제1항에 있어서, 상기 유리층은 산화물 환산시 천이금속을 0.01~5중량% 함유한 것을 특징으로 하는 회로기판.
  7. 제1항에 있어서, 상기 유리층은 산화물 환산시 알루미늄산화물을 0.02~5중량% 함유한 것을 특징으로 하는 회로기판.
  8. 제6항에 있어서, 상기 천이금속은 티타늄, 크로뮴, 철, 코발트, 마가니스, 니켈, 구리, 지코늄 또는 탄탈륨인 것을 특징으로 하는 회로기판.
  9. 제1항에 있어서, 상기 금속판은 구리로 구성되고, 유리는 실온으로부터 300℃에서의 평균열확장율이 7~13×10-6/℃인 것을 특징으로 하는 회로기판.
  10. 제1항에 있어서, 상기 금속판은 알루미늄으로 구성되고, 유리는 실온으로부터 300℃에서의 평균열확장율이 10~18×10-6/℃인 것을 특징으로 하는 회로기판.
  11. 제1항에 있어서, 상기 금속판은 니켈로 구성되고, 유리는 실온으로부터 300℃에서의 평균열확장율이 5~10×10-6/℃인 것을 특징으로 하는 회로기판.
  12. 제1항에 있어서, 상기 질화규소 세라믹판/금속판의 두께비는 5~1, 금속판/유리층의 두께비는 2~40인 것을 특징으로 하는 회로기판.
  13. 제1항에 있어서, 상기 질화규소 세라믹판은 비산화분위기에서 가열되어 얻어지는 것을 특징으로 하는 회로기판.
  14. 제1항에 있어서, 상기 유리층은 스핀코팅법에 의해 질화규소 세라믹판상에 코팅된 유리현탁부를 가열함으로써 제공되는 것을 특징으로 하는 회로기판.
  15. 제1항에 있어서, 상기 유리층은 디핑법에 의해 질화규소 세라믹판상에 코팅된 유리현탁부를 가열함으로써 제공되는 것을 특징으로 하는 회로기판.
  16. 제1항에 있어서, 반도체장치는 제1항에 따른 기판을 사용하는 회로기판.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960042429A 1995-09-28 1996-09-25 질화규소 세라믹회로기판 및 이것을 이용한 반도체장치 KR100244823B1 (ko)

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JP8070012A JPH09153568A (ja) 1995-09-28 1996-03-26 窒化珪素セラミック回路基板および半導体装置
JP96-070012 1996-03-26

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