KR970018409A - 반도체소자의 금속배선 형성방법 - Google Patents

반도체소자의 금속배선 형성방법 Download PDF

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KR970018409A
KR970018409A KR1019950031258A KR19950031258A KR970018409A KR 970018409 A KR970018409 A KR 970018409A KR 1019950031258 A KR1019950031258 A KR 1019950031258A KR 19950031258 A KR19950031258 A KR 19950031258A KR 970018409 A KR970018409 A KR 970018409A
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South Korea
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pattern
film
tungsten
aluminum
etching
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KR1019950031258A
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KR100374229B1 (ko
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이승욱
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김주용
현대전자산업 주식회사
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Priority to KR1019950031258A priority Critical patent/KR100374229B1/ko
Publication of KR970018409A publication Critical patent/KR970018409A/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 금속배선 식각방법에 관한 것으로 특히, 디렉트 워드라인 스트랩핑(direct wordline strapping)에 있어서, 마이크로 로딩 효과(micro loading effect)를 해소하기 위하여 텅스텐과 알루미늄과의 선택비가 높은 것을 이용하여 텅스텐, 알루미늄, 텅스텐을 차례로 증착하고, 식각공정으로 패턴을 형성하는 방법이다.

Description

반도체소자의 금속배선 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도 내지 제6도는 본 발명의 기술에 의해 반도체소자의 금속배선 형성방법을 도시한 단면도.

Claims (10)

  1. 반도체기판의 상부에 산화절연막, 베리어금속막, 제1 텅스텐막, 알루미늄막, 제2 텅스텐막, 비반사막을 차례로 적층하는 단계와, 그 상부에 금속배선 마스크용 감광막패턴을 형성하는 단계와, 상기 금속배선 마스크용 감광막패턴으로 비반사막과 제2 텅스텐막을 식각하여 비반사막패턴과 제2 텅스텐패턴을 형성하는 단계와, 상기 금속배선 마스크용 감광막패턴을 제거하는 단계와, 제2 텅스텐패턴을 마스크로 비반사막패턴과 노출된 알루미늄막을 식각하여 알루미늄패턴을 형성하는 단계와, 상기 알루미늄패턴을 마스크로 제2 텅스텐패턴과 제1 텅스텐패턴을 식각하여 제1 텅스텐패턴을 형성하는 단계와, 상기 제1 텅스턴패턴을 마스크로 상기 알루미늄패턴과 노출된 베리어금속막을 식각하여 제1 텅스턴패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 금속배선 식각방법.
  2. 제1항에 있어서, 상기 제1 텅스텐막은 1000 내지 3500Å의 두께로 증착되는 것을 특징으로 하는 반도체소자의 금속배선 식각방법.
  3. 제1항에 있어서, 상기 알루미늄막은 1000 내지 2000Å의 두께로 증착되는 것을 특징으로 하는 반도체소자의 금속배선 식각방법.
  4. 제1항에 있어서, 제2 텅스텐막은 2000 내지 3000Å 두께로 증착되는 것을 특징으로 하는 반도체소자의 금속배선 식각방법.
  5. 제1항에 있어서, 비반사막은 200 내지 1500Å 두께의 TiN막으로 증착되는 것을 특징으로 하는 반도체소자의 금속배선 식각방법.
  6. 제1항에 있어서, 상기 제2 텅스텐막 식각시 클로린(clorine)과 플로오린(fluorine)을 주 식각가스로 이용하는 것을 특징으로 하는 반도체소자의 금속배선 식각방법.
  7. 제1항에 있어서, 상기 알루미늄막 식각시 비반사막이 식각되어 제거되는 것을 특징으로 하는 반도체소자의 금속배선 식각방법.
  8. 제1항에 있어서, 제2 텅스텐패턴과 제1 텅스텐막을 식각할 때 플루오린을 주 식각가스로 하는 것을 특징으로 하는 반도체소자의 금속배선 식각방법.
  9. 제1항에 있어서, 상기 알루미늄패턴을 마스크로하여 제2 텅스텐패턴과 제1 텅스텐패턴을 과도식각하는 것을 특징으로 하는 반도체소자의 금속배선 식각방법.
  10. 제1항에 있어서, 상기 베리어금속막은 클로린을 주 가스로 하여 식각하는 것을 특징으로 하는 반도체소자의 금속배선 식각방법.
KR1019950031258A 1995-09-21 1995-09-21 반도체소자의금속배선형성방법 KR100374229B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950031258A KR100374229B1 (ko) 1995-09-21 1995-09-21 반도체소자의금속배선형성방법

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Application Number Priority Date Filing Date Title
KR1019950031258A KR100374229B1 (ko) 1995-09-21 1995-09-21 반도체소자의금속배선형성방법

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KR970018409A true KR970018409A (ko) 1997-04-30
KR100374229B1 KR100374229B1 (ko) 2003-05-12

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KR1019950031258A KR100374229B1 (ko) 1995-09-21 1995-09-21 반도체소자의금속배선형성방법

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JPH04206528A (ja) * 1990-11-30 1992-07-28 Hitachi Ltd 半導体装置における配線構造

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