KR970004619Y1 - Semiconductor chip - Google Patents

Semiconductor chip Download PDF

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Publication number
KR970004619Y1
KR970004619Y1 KR2019940003555U KR19940003555U KR970004619Y1 KR 970004619 Y1 KR970004619 Y1 KR 970004619Y1 KR 2019940003555 U KR2019940003555 U KR 2019940003555U KR 19940003555 U KR19940003555 U KR 19940003555U KR 970004619 Y1 KR970004619 Y1 KR 970004619Y1
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KR
South Korea
Prior art keywords
chip
inner lead
groove
lead
bonded
Prior art date
Application number
KR2019940003555U
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Korean (ko)
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KR950025923U (en
Inventor
정관호
Original Assignee
현대전자산업 주식회사
김주용
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Priority to KR2019940003555U priority Critical patent/KR970004619Y1/en
Publication of KR950025923U publication Critical patent/KR950025923U/en
Application granted granted Critical
Publication of KR970004619Y1 publication Critical patent/KR970004619Y1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용없음.None.

Description

반도체 칩Semiconductor chip

제 1 도는 종래의 리드온칩 패키지의 단면도1 is a cross-sectional view of a conventional lead-on chip package

제 2 도는 종래의 리드온칩 패키지의 요부 부분확대 평면도2 is a partially enlarged plan view of a conventional lead-on chip package

제 3 도는 본 고안의 리드온칩 패키지의 평면도3 is a plan view of the lead-on chip package of the present invention

제 4 도는 제 3 도의 A부의 세부 평면도4 is a detailed plan view of part A of FIG.

제 5 도는 제 4 도의 B-B 단면도이다.5 is a cross-sectional view taken along line B-B in FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 칩 2 : 테이프1: chip 2: tape

3 : 내부리드 6 : 그루브실용신안의 상세한 설명3: Internal lead 6: Detailed description of groove utility model

본 고안은 그루브를 형성한 반도체 칩에 관한 것으로, 반도체 장치의 제조와 관련된 것으로 특히 리드온칩패키지 제조에 관한 것이다.The present invention relates to a semiconductor chip in which grooves are formed, and more particularly to manufacturing a semiconductor device, and more particularly to manufacturing a lead-on chip package.

종래의 리드온칩 패키지에서는 제 1 도에 도시한 바와 같이 칩(1)과 ; 칩(1)과 내부리드(3)을 접착하는 테이프(2)와 ; 내부리드(3)과 ; 와이어(4) 및 ; 봉지제(5)를 포함하여 구성된다.In the conventional lead-on chip package, as shown in FIG. 1, the chip 1 and; A tape 2 for adhering the chip 1 and the inner lead 3; Internal lead 3 and; Wire 4 and; It comprises a sealing agent 5.

상기 종래의 리드온칩 패키지를 조립하는 과정에서 칩(1)위에 테이프(2)를 개재시켜 내부리드(3)와 어태치되는 상태의 부분확대 평면도는 제 2 도와 같이 도시할 수 있는바, 다이 어태치시에 칩(1)과 칩(1)을 내부리드(3)에 접착하는 테이프(2) 사이에 에어가 갇히게되어 내부 보이드(7)가 발생하여 패키지 크랙 및 신용도 시험시 열악한 조건을 제공하는 원인이 되는 문제점이 있었다.In the process of assembling the conventional lead-on-chip package, a partially enlarged plan view of the state in which the lead 2 is attached to the inner lead 3 by interposing the tape 2 on the chip 1 may be illustrated as a second diagram. Air is trapped between the chip 1 and the tape 2 adhering the chip 1 to the inner lead 3 to the inner cylinder, causing an internal void 7 to provide poor conditions in testing the package crack and reliability. There was a problem becoming.

본 고안은 이러한 점을 감안하여 내부 보이드를 제거하기위하여 칩의 상부의 스핀 코팅된 표면을 부분적으로 에칭을 실시하여 테이프와 접착되는 칩의 상부표면에 그루브를 형성하는 것을 특징으로 하는 것이다.In view of this, the present invention is characterized by forming a groove on the upper surface of the chip which is adhered to the tape by partially etching the spin-coated surface of the upper part of the chip to remove the internal voids.

이하 도면을 참조로하여 상세히 설명한다.Hereinafter, with reference to the drawings will be described in detail.

본 고안의 리드온칩 패키지 평면도는 제 3 도에 도시한 바와 같이 상부표면에 그루브를 형성한 칩(1)과 ; 그루브를 형성한 칩(1)과 내부리드(3)를 접착시키는 테이프(2)와 ; 내부리드(3)로 구성된다.The plan view of a lead-on chip package according to the present invention includes a chip 1 having a groove formed on an upper surface thereof as shown in FIG. A tape 2 for adhering the chip 1 having the groove formed thereon and the inner lead 3; It consists of an inner lead 3.

상기 제 3 도의 A부의 상세 평면도는 제 4 도와 같이 도시할 수 있는바, 테이프(2)가 접착될 칩(1)상부의 스핀 코팅된 표면을 에칭하여 형성한 에어 벤트 기능을 수행하는 그루부(6)는 내부리드(3) 접착되는 칩(1)의 상부표면의 에지부분은 내부리드(3)와 수평방향으로 형성되고, 내부리드(3)가 접착되는 칩(1)의 상부표면의 중앙부분은 내부리드(3)의 수직방향으로 형성되고, 내부리드(3)의 끝부분이 접착되는 칩의 상부표면은 내부리드(3)와 수평방향으로 형성되며, 상기 그루부(6)는 상호 연결되도록 형성되어 다이어태치 공정으로 운반되어 칩(1)에 테이프(2)가 접착되고 내부리드(3)가 접착되는 다이어태치공정시에 내부 보이드를 제거하도록 하는 것이다. 상기 제 4 도의 B-B 단면도는 제 5 도와 같이 도시할 수 있는 바, 칩(1)의 상부표면에는 그루부(6)가 형성되어 있으므로 테이프(2) 접착시 에어가 쉽게 그루부(6)를 따라 배출되면서 테이프(2)의 접착제가 그루부(6)를채워 내부 보이드가 제거된 패키지를 얻을 수 있다.A detailed plan view of part A of FIG. 3 may be illustrated as a fourth diagram, wherein a groove for performing an air vent function formed by etching a spin-coated surface on an upper portion of the chip 1 to which the tape 2 is to be bonded ( 6) the edge portion of the upper surface of the chip 1 to be bonded to the inner lead 3 is formed in the horizontal direction with the inner lead 3, the center of the upper surface of the chip 1 to which the inner lead 3 is bonded The part is formed in the vertical direction of the inner lead 3, the upper surface of the chip to which the end of the inner lead 3 is bonded is formed in the horizontal direction with the inner lead 3, the groove 6 is mutually It is formed to be connected to be carried in the die attach process to remove the internal void during the die attach process in which the tape 2 is bonded to the chip 1 and the inner lead 3 is bonded. The cross-sectional view taken along line BB of FIG. 4 may be illustrated as the fifth diagram. Since the groove 6 is formed on the upper surface of the chip 1, air is easily along the groove 6 when the tape 2 is bonded. As it is ejected, the adhesive of the tape 2 fills the groove 6 to obtain a package from which the internal voids have been removed.

또한 칩의 상부표면에 제작된 그루브로 인하여 봉지제와 칩의 결합력을 강화시켜준다.In addition, the groove formed on the upper surface of the chip enhances the bonding force between the encapsulant and the chip.

이상에서 살펴본 바와 같이 본 고안에 따르면 다이어태치시 내부 보이드를 제거하고 봉지제와 첩의 결합력이 강화됨으로 인해 패키지의 질과 신뢰성을 향상시키고, 패키지 크랙 및 디레미네이션을 방지하는 효과가 있다.As described above, according to the present invention, internal voids are removed during the die attach, and the bonding force between the encapsulant and the chirp is enhanced, thereby improving the quality and reliability of the package and preventing package cracks and delamination.

Claims (2)

리드온칩 패키지에 있어서, 테이프(2)가 접착될 칩(1)상부의 스핀 코팅된 표면이 에칭되어 그루부(6)가형성된 것을 특징으로 하는 반도체 칩.A lead-on chip package, wherein the spin-coated surface on top of the chip (1) to which the tape (2) is to be bonded is etched to form a groove (6). 제 1 항에 있어서,The method of claim 1, 내부리드(3)가 접착되는 칩(1) 상부표면의 에지부분의 그루부(6)는 내부리드(3)와 수평방향으로 형성되고, 내부리드(3)가 접착되는 칩(1)의 상부표면의 중앙부분의 그루부(6)는 내부리드(3)와 수직방향으로 형성되고, 내부리드(3)의 끝부분이 접착되는 칩(1)의 상부표면의 그루부(6)는 내부리드(3)와 수평방향으로 형성되며, 각 그루부(6)는 상호 연결되도록 이루어짐을 특징으로 하는 반도체 칩.The groove 6 of the edge portion of the upper surface of the chip 1 to which the inner lead 3 is bonded is formed in a horizontal direction with the inner lead 3 and the upper part of the chip 1 to which the inner lead 3 is bonded. The groove 6 of the center portion of the surface is formed in a direction perpendicular to the inner lead 3, and the groove 6 of the upper surface of the chip 1 to which the end of the inner lead 3 is bonded is the inner lead. It is formed in the horizontal direction with the (3), the semiconductor chip, characterized in that each groove portion 6 is made to be interconnected.
KR2019940003555U 1994-02-25 1994-02-25 Semiconductor chip KR970004619Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019940003555U KR970004619Y1 (en) 1994-02-25 1994-02-25 Semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019940003555U KR970004619Y1 (en) 1994-02-25 1994-02-25 Semiconductor chip

Publications (2)

Publication Number Publication Date
KR950025923U KR950025923U (en) 1995-09-18
KR970004619Y1 true KR970004619Y1 (en) 1997-05-13

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KR2019940003555U KR970004619Y1 (en) 1994-02-25 1994-02-25 Semiconductor chip

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KR950025923U (en) 1995-09-18

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