KR100451488B1 - Semiconductor package having reduced size and thin thickness and fabricating method thereof - Google Patents

Semiconductor package having reduced size and thin thickness and fabricating method thereof Download PDF

Info

Publication number
KR100451488B1
KR100451488B1 KR1019960067216A KR19960067216A KR100451488B1 KR 100451488 B1 KR100451488 B1 KR 100451488B1 KR 1019960067216 A KR1019960067216 A KR 1019960067216A KR 19960067216 A KR19960067216 A KR 19960067216A KR 100451488 B1 KR100451488 B1 KR 100451488B1
Authority
KR
South Korea
Prior art keywords
semiconductor chip
sidewall
attached
semiconductor package
die pad
Prior art date
Application number
KR1019960067216A
Other languages
Korean (ko)
Other versions
KR19980048613A (en
Inventor
남택환
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1019960067216A priority Critical patent/KR100451488B1/en
Publication of KR19980048613A publication Critical patent/KR19980048613A/en
Application granted granted Critical
Publication of KR100451488B1 publication Critical patent/KR100451488B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE: A semiconductor package and a fabricating method thereof are provided to reduce a size of a package to a chip by adhering a plurality of sidewall leads on both sidewalls of a substrate. CONSTITUTION: A metal pad(15a) is formed on a semiconductor chip(15). The semiconductor chip is adhered on a die pad(11). Both sidewalls of the die pad have respectively a tapering structure which is reduced from a lower part to an upper part. A plurality of sidewall leads(13a,13b,13c) are adhered alternately on the sidewalls of the die pad. The sidewall leads increase gradually in their heights to form a stepped part. A wire(16) is used for connecting the metal pad to the sidewall leads.

Description

반도체 패키지 및 그 제조방법Semiconductor package and manufacturing method

본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로, 보다 구체적으로는 경박단소형화된 반도체 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly to a light and small sized semiconductor package and a method for manufacturing the same.

종래 일반적으로 알려지고 있는 플라스틱 반도체 패키지는, 하나의 반도체 칩을 에폭시 몰딩 컴파운드 등과 같은 수지로 몰딩한 구조로 되어 있으며, 또한 기판에 실장하기 위한 아웃 리드를 갖는 리드 프레임이라는 구조물을 이용하여 신호전달 체계를 이루고 있다.Plastic semiconductor packages generally known in the art have a structure in which one semiconductor chip is molded with a resin such as an epoxy molding compound, and a signal transmission system using a structure called a lead frame having an out lead for mounting on a substrate. To achieve.

상기와 같은 플라스틱 반도체 패키지의 전형적인 한 예가 도 1에 도시되어 있는 바, 이를 간단히 살펴보면 다음과 같다.A typical example of such a plastic semiconductor package is shown in FIG. 1, which is briefly described as follows.

도면은 일반적인 플라스틱 반도체 패키지의 구조를 나타낸 단면도로서, 도면에서 참조 부호 1은 반도체 칩, 2는 상기 반도체 칩(1)을 지지함과 아울러 상기 칩(1)의 외부로의 전기적인 접속 경로를 이루는 리드 프레임, 3은 상기 리드 프레임(2)의 인너 리드(2a)와 반도체 칩(1)을 전기적으로 접속, 연결시키는 금속 와이어, 4는 상기 칩(1), 리드 프레임(2)의 인너 리드(2a) 및 금속 와이어(3)를 봉하여 막는 봉지체를 각각 보인 것이다.FIG. 3 is a cross-sectional view illustrating a structure of a general plastic semiconductor package, in which reference numeral 1 denotes a semiconductor chip, 2 supports the semiconductor chip 1, and forms an electrical connection path to the outside of the chip 1. Lead frame 3 is a metal wire for electrically connecting and connecting the inner lead 2a of the lead frame 2 and the semiconductor chip 1, and 4 is the inner lead of the chip 1 and the lead frame 2. 2a) and the sealing body which seals and closes the metal wire 3 are respectively shown.

도시된 바와 같이, 상기 반도체 칩(1)은 리드 프레임(2)의 패들(2c)위에 접착제의 개재하에 부착, 고정되어 있고, 상기 반도체 칩(1)과 리드 프레임(2)의 인너 리드(2a)는 금속 와이어(3)에 의해 전기적으로 접속, 연결되어 있다. 이와 같이된 반도체 칩(1), 리드 프레임(2)의 인너 리드(2a) 및 금속 와이어(3)를 포함하는 일정 면적이 플라스틱 수지에 의해 밀봉되어 대략 장방형의 패키지 몸체, 즉 봉지체(4)를 형성하고 있다. 또한 상기 봉지체(4)의 양측에는 기판에의 실장을 위한 아웃 리드(2b)가 일정 간격을 유지하여 돌출, 형성되어 있다.As shown, the semiconductor chip 1 is attached and fixed on the paddle 2c of the lead frame 2 with the adhesive interposed therebetween, and the inner lead 2a of the semiconductor chip 1 and the lead frame 2 is fixed. ) Is electrically connected and connected by the metal wire 3. A predetermined area including the semiconductor chip 1, the inner lead 2a of the lead frame 2, and the metal wire 3 is sealed by a plastic resin to form a substantially rectangular package body, that is, the encapsulation 4. To form. Further, on both sides of the encapsulation member 4, the out leads 2b for mounting on the substrate are protruded and formed at a constant interval.

이러한 종래의 플라스틱 반도체 패키지는 반도체 칩(1)을 리드 프레임(2)의 패들(2c)위에 부착하는 다이 본딩 공정과, 상기 패들(2c)위의 반도체 칩(1)과 리드 프레임(2)의 인너 리드(2a)를 금속 와이어(3)를 이용하여 전기적으로 연결하는 와이어 본딩 공정과, 상기 칩(1), 인너 리드(2a) 및 금속 와이어(3)를 포함하는 일정면적을 봉하여 막는 봉지체(4)를 형성하는 몰딩 공정과, 상기 리드 프레임(2)의 각 리드를 지지하고 있는 댐바(도시되지 않음) 등을 절단하여 각각의 독립된 패키지로 분리함과 아울러 봉지체(4)의 양측으로 돌출된 아웃 리드(2b)를 소정 형상으로 절곡 형성하는 트림/포밍 공정을 통하여 제조되며, 이와 같이 제조된 반도체 패키지는 그의 아웃 리드(2b)를 기판의 패턴에 일치시켜 리플로워 솔더링하는 것에 의하여 실장되어 전기적인 신호를 입,출력하는 등의 작용을 하게 된다.Such a conventional plastic semiconductor package includes a die bonding process of attaching the semiconductor chip 1 to the paddle 2c of the lead frame 2, and the semiconductor chip 1 and the lead frame 2 of the paddle 2c. A wire bonding process for electrically connecting the inner lead 2a with the metal wire 3, and a rod sealing and blocking a predetermined area including the chip 1, the inner lead 2a, and the metal wire 3; The molding process for forming the housing 4, the dam bar (not shown) supporting each lead of the lead frame 2, etc. are cut and separated into respective independent packages, and both sides of the sealing body 4 Is manufactured through a trim / forming process of bending out leads 2b protruding into a predetermined shape, and the semiconductor package manufactured as described above is reflowed and soldered by matching the out leads 2b to a pattern of a substrate. Mounted and receiving electrical signals, Is a function, such as strength.

그러나, 상기한 바와 같은 종래의 일반적인 반도체 패키지에 있어서는, 패키지 사이즈 대비 칩 점유율에 한계가 있음으로써 대용량의 패키지 구현이 어렵다는 문제가 있었다.However, in the conventional general semiconductor package as described above, there is a problem that it is difficult to implement a large-capacity package because there is a limit in chip occupancy compared to the package size.

또 종래의 싱글 플라스틱 패키지는 칩의 외부와의 전기적 도통 경로로써 알루미늄이나 골드 등과 같은 금속세선을 사용하고, 리드 프레임 또는 기판에 본딩함으로써 금속세선으로 인한 신뢰성에 문제를 발생시키는 등 품질 저하를 초래하는 문제가 있었다.In addition, the conventional single plastic package uses a thin metal wire such as aluminum or gold as an electrical conduction path to the outside of the chip, and causes a quality deterioration such as a problem in reliability due to the fine metal wire by bonding to a lead frame or a substrate. There was a problem.

본 발명은 상기와 같은 종래의 반도체 패키지가 가지는 제반 문제점을 해소하기 위하여 창안한 것으로, 패키지의 대용량화 및 경박단소형화를 이룰 수 있는 반도체 패키지를 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve all the problems of the conventional semiconductor package as described above, and an object thereof is to provide a semiconductor package capable of achieving a large capacity and light and small size of the package.

또한 본 발명의 다른 목적은 상기와 같은 반도체 패키지의 제조방법을 제공하는 것을 목적으로 한다.Another object of the present invention is to provide a method of manufacturing a semiconductor package as described above.

도 1은 종래 기술에 따른 반도체 패키지의 단면도.1 is a cross-sectional view of a semiconductor package according to the prior art.

도 2A 내지 2E는 본 발명에 따른 반도체 패키지의 제조방법을 설명하기 위한 각 공정 별 단면도.2A to 2E are cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor package according to the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

11 : 기판 12 : 접착 테이프11: substrate 12: adhesive tape

13 : 측벽 리드 14 : 접착층13: side wall lead 14: adhesive layer

15 : 반도체 칩 16 : 와이어15 semiconductor chip 16: wire

17 : 봉지체17: sealing body

상기한 본 발명의 목적을 달성하기 위하여, 본 발명의 반도체 패키지는, 금속 패드가 형성된 반도체 칩; 상기 반도체 칩이 부착되는 기판; 상기 기판의 양측에 접착 수단에 의하여 부착되는 측벽 리드; 상기 반도체 칩의 금속 패드와 상기 측벽 리드를 연결하는 와이어를 포함하는 것을 특징으로 한다.In order to achieve the above object of the present invention, a semiconductor package of the present invention, a semiconductor chip formed metal pad; A substrate to which the semiconductor chip is attached; Sidewall leads attached to both sides of the substrate by adhesive means; And a wire connecting the metal pad and the sidewall lead of the semiconductor chip.

또한, 본 발명에 따른 반도체 패키지의 제조방법은, 기판을 준비하는 단계; 상기 기판의 양측벽에 접착 테이프를 형성하고, 상기 접착 테이프와 접착되도록 측벽 리드를 형성하는 단계; 상기 기판상에 금속 패드를 구비하는 반도체 칩을 부착하는 단계; 상기 반도체 칩의 금속 패드와, 상기 측벽 리드간을 와이어 본딩하는 단계를 포함하는 것을 특징으로 한다.In addition, the method of manufacturing a semiconductor package according to the present invention includes the steps of preparing a substrate; Forming an adhesive tape on both sidewalls of the substrate, and forming sidewall leads to adhere to the adhesive tape; Attaching a semiconductor chip having a metal pad on the substrate; And wire bonding between the metal pad of the semiconductor chip and the sidewall lead.

본 발명에 의하면, 반도체칩이 부착되는 기판의 양측벽에 소정의 크기로 부착된 다수개의 측벽 리드가 구비되어, 칩 대비 패키지 사이즈를 줄일수 있다.According to the present invention, a plurality of sidewall leads attached to a predetermined size on both side walls of the substrate to which the semiconductor chip is attached is provided, thereby reducing the package size compared to the chip.

[실시예]EXAMPLE

이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도면 도 2A 내지 2는 본 발명에 따른 반도체 패키지의 제조방법을 설명하기 위한 각 공정 별 단면도로서, 도면 부호 11은 기판이고, 12는 기판 측벽에 리드를 부착시키기 위한 리드용 접착 테이프이고, 13은 리드용 접착층에 의하여 기판에 부착되는 측벽 리드이고, 14는 접착층이고, 15는 반도체 칩이다. 또한, 16은 와이어를 나타내고, 17은 봉지체를 나타낸다.2A through 2 are cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor package according to the present invention, wherein reference numeral 11 is a substrate, and 12 is an adhesive tape for lead for attaching a lead to sidewalls of the substrate. 13 is a side wall lead attached to a board | substrate by the adhesive bond layer for leads, 14 is an adhesive layer, and 15 is a semiconductor chip. In addition, 16 represents a wire and 17 represents a sealing body.

도 2A를 참조하여, 반도체 칩이 놓여질 다이 패드(11)가 준비된다. 이때, 다이 패드(11)는 하부에서 상부로 갈수록 그 폭이 감소되는 테이퍼(tapper) 형상으로 형성된다.2A, a die pad 11 on which a semiconductor chip is to be placed is prepared. At this time, the die pad 11 is formed in a taper shape whose width decreases from the bottom to the top.

그 후, 도 2B에 도시된 바와 같이, 제 1 접착 테이프(12a)는 다이 패드(11)의 양측벽에 형성되고, 제 1 리드(13a)는 제 1 접착 테이프(12a)에 의하여, 기판의 양측벽에 부착·형성된다. 이때, 제 1 리드(13)의 높이는 상기 기판의 높이 보다 약간 크도록 형성된다.Thereafter, as shown in FIG. 2B, the first adhesive tape 12a is formed on both side walls of the die pad 11, and the first lead 13a is formed by the first adhesive tape 12a. It is attached to and formed on both side walls. At this time, the height of the first lead 13 is formed to be slightly larger than the height of the substrate.

그후, 도 2C를 참조하여, 접착 테이프(12b, 12c)와 리드(13b, 13c...)를 번갈아 제 1 리드가 형성된 기판 양측벽에 형성되어, 다수개의 측벽 리드(13a, 13b, 13c)가 다이 패드(11)의 측벽에 형성된다.Subsequently, referring to FIG. 2C, the adhesive tapes 12b and 12c and the leads 13b and 13c. Is formed on the sidewall of the die pad 11.

그리고 나서, 도 2D에 도시된 바와 같이, 다이 패드(11)상에 금속 패드가 구비된 반도체 칩(15)을 접착시키기 위하여, 접착층(14)이 형성되고, 접착층(14) 상에 금속 패드(15a)를 구비한 반도체 칩(15)을 얹은 후, 칩 어테치(attach) 공정을 진행하여, 반도체 칩(15)이 다이 패드(11) 상에 부착된다.Then, as shown in FIG. 2D, in order to bond the semiconductor chip 15 with the metal pad on the die pad 11, an adhesive layer 14 is formed, and the metal pad ( After mounting the semiconductor chip 15 provided with 15a, the chip attach process is performed, and the semiconductor chip 15 is attached on the die pad 11.

그 후, 도 2E에서와 같이, 반도체 칩(15)과 다수개의 리드(13a, 13b, 13c)를 금속 와이어(16)를 이용하여 전기적으로 연결시킨다음, 반도체 칩(11), 측벽 리드(13a, 13b, 13c) 및 금속 와이어(16)를 포함하는 일정 면적을 공지된 몰딩 공정에 의하여 봉지체(17)가 형성되어, 본 발명에 따른 패키지가 완성된다.Thereafter, as shown in FIG. 2E, the semiconductor chip 15 and the plurality of leads 13a, 13b, and 13c are electrically connected using the metal wire 16, and then the semiconductor chip 11 and the sidewall leads 13a. The encapsulation body 17 is formed by a known molding process in a predetermined area including the metal wire 16, 13b, 13c, and the package according to the present invention is completed.

이상에서 자세히 설명된 바와 같이, 본 발명은 반도체칩이 부착되는 기판의 양측벽에 소정의 크기로 부착된 다수개의 측벽 리드가 구비되어, 칩 대비 패키지사이즈를 줄일수 있다.As described in detail above, the present invention is provided with a plurality of sidewall leads attached to a predetermined size on both side walls of the substrate to which the semiconductor chip is attached, thereby reducing the package size compared to the chip.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (4)

금속 패드가 형성된 반도체 칩;A semiconductor chip having a metal pad formed thereon; 상기 반도체 칩이 부착되며, 양측벽이 하부에서 상부로 갈수록 그 폭이 감소되는 테이퍼 형상으로 형성된 다이 패드;A die pad to which the semiconductor chip is attached and formed in a tapered shape in which widths of both side walls thereof are reduced from the lower part to the upper part; 상기 다이 패드의 테이퍼진 양측벽에 접착 수단에 의하여 측면 경사지도록 교대로 배치 및 부착되는 적어도 하나 이상을 가지며, 최종 부착된 것이 최초 부착된 것에 비해 높이가 점차로 커져 측면 단차가 발생되는 측벽 리드;Sidewall leads having at least one or more alternately arranged and attached to the tapered sidewalls of the die pad by side bonding means, and having a height higher than that of the first attached one so as to have a side step; 상기 반도체 칩의 금속 패드와 상기 측벽 리드들을 연결하는 와이어를 포함하는 것을 특징으로 하는 반도체 패키지.And a wire connecting the metal pad of the semiconductor chip and the sidewall leads. 제 1 항에 있어서, 상기 절연 수단은 절연 테이프인 것을 특징으로 하는 반도체 패키지.The semiconductor package according to claim 1, wherein said insulating means is an insulating tape. 제 1 항에 있어서, 상기 측벽 리드의 높이는 기판의 높이보다 큰 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein a height of the sidewall leads is greater than a height of a substrate. 양측벽이 테이퍼 형태를 가진 다이 패드를 준비하는 단계;Preparing a die pad having a tapered shape at both side walls; 상기 다이 패드의 테이퍼진 양측벽에 접착테이프에 의하여 측면 경사지도록 적어도 하나 이상의 측벽 리드를 교대로 배치 및 부착하되, 상기 측벽 리드는 최종부착된 것이 최초 부착된 것에 비해 높이가 점차로 커져 측면 단차가 발생되는 단계;At least one sidewall lead is alternately arranged and attached to both tapered sidewalls of the die pad by an adhesive tape, and the sidewall lead is gradually increased in height compared to the first one to which the final side is attached, thereby causing side step difference. Becoming; 상기 다이 패드 상에 금속 패드를 구비하는 반도체 칩을 부착하는 단계;Attaching a semiconductor chip having a metal pad on the die pad; 상기 반도체 칩의 금속 패드와, 상기 측벽 리드들 간을 와이어 본딩하는 단계를 포함하는 것을 특징으로 하는 반도체 패키지의 제조방법.And wire-bonding the metal pad of the semiconductor chip and the sidewall leads.
KR1019960067216A 1996-12-18 1996-12-18 Semiconductor package having reduced size and thin thickness and fabricating method thereof KR100451488B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960067216A KR100451488B1 (en) 1996-12-18 1996-12-18 Semiconductor package having reduced size and thin thickness and fabricating method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960067216A KR100451488B1 (en) 1996-12-18 1996-12-18 Semiconductor package having reduced size and thin thickness and fabricating method thereof

Publications (2)

Publication Number Publication Date
KR19980048613A KR19980048613A (en) 1998-09-15
KR100451488B1 true KR100451488B1 (en) 2004-11-26

Family

ID=37366973

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960067216A KR100451488B1 (en) 1996-12-18 1996-12-18 Semiconductor package having reduced size and thin thickness and fabricating method thereof

Country Status (1)

Country Link
KR (1) KR100451488B1 (en)

Also Published As

Publication number Publication date
KR19980048613A (en) 1998-09-15

Similar Documents

Publication Publication Date Title
KR0152901B1 (en) Plastic package and method for manufacture thereof
US6410979B2 (en) Ball-grid-array semiconductor device with protruding terminals
US5619065A (en) Semiconductor package and method for assembling the same
JPH09252014A (en) Manufacturing method of semiconductor element
US6127206A (en) Semiconductor device substrate, lead frame, semiconductor device and method of making the same, circuit board, and electronic apparatus
US20030038347A1 (en) Stackable-type semiconductor package
US20040084757A1 (en) Micro leadframe package having oblique etching
KR100451488B1 (en) Semiconductor package having reduced size and thin thickness and fabricating method thereof
US6858474B1 (en) Wire bond package and packaging method
US20030082855A1 (en) Board frame, method for fabricating thereof and method for fabricating semiconductor apparatus
JPS61241954A (en) Semiconductor device
KR100220244B1 (en) Stack package using solder bump
KR0119730Y1 (en) Bottom Leaded Semiconductor Package
KR100221918B1 (en) Chip scale package
KR100819794B1 (en) Lead-frame and method for manufacturing semi-conductor package using such
KR0134650B1 (en) Thin film semiconductor package and the manufacture method
KR200159861Y1 (en) Semiconductor package
KR100364842B1 (en) Semiconductor package and method of manufacturing the same
KR100356787B1 (en) Semiconductor Package Manufacturing Method
JPH0750384A (en) Multichip semiconductor device and manufacture thereof
KR0135889Y1 (en) Complex-type semiconductor package
KR100345162B1 (en) Ball grid array package
KR100357876B1 (en) semiconductor package and its manufacturing method
KR950008240B1 (en) Semiconductor package
KR100460072B1 (en) Semiconductor Package

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20130821

Year of fee payment: 10

FPAY Annual fee payment

Payment date: 20140820

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee