KR970003839A - Multilayer wiring structure of semiconductor device and method of forming the same - Google Patents

Multilayer wiring structure of semiconductor device and method of forming the same Download PDF

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Publication number
KR970003839A
KR970003839A KR1019950017157A KR19950017157A KR970003839A KR 970003839 A KR970003839 A KR 970003839A KR 1019950017157 A KR1019950017157 A KR 1019950017157A KR 19950017157 A KR19950017157 A KR 19950017157A KR 970003839 A KR970003839 A KR 970003839A
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KR
South Korea
Prior art keywords
conductive layer
upper conductive
forming
region
insulating layer
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KR1019950017157A
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Korean (ko)
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KR0155834B1 (en
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노병혁
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김광호
삼성전자 주식회사
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Priority to KR1019950017157A priority Critical patent/KR0155834B1/en
Publication of KR970003839A publication Critical patent/KR970003839A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

반도체장치의 다층 배선구조 및 그 형성방법에 대해 기재되어 있다.A multilayer wiring structure of a semiconductor device and a method of forming the same are described.

이는, 반도체기판 상에 형성된 하부 도전층, 하부 도전층 상에 형성된 절연층, 절연층 상에 형성되어 있으며, 그 사이의간격이 측벽 스페이서 두께의 두 배보다 작은 제1영역과, 그 사이의 간격이 측벽 스페이서 두께의 두 배보다 큰 제2영역을 갖는 상부 도전층, 상부 도전층의 측벽에 형성된 측벽스페이서 및 제2영역에 위치하고, 측벽 스페이서에 자기정합된콘택홀을 구비하는 것을 특징으로 한다.It is formed on the lower conductive layer formed on the semiconductor substrate, the insulating layer formed on the lower conductive layer, and the insulating layer, the first region having a gap therebetween being less than twice the thickness of the sidewall spacer, and the gap therebetween. And an upper conductive layer having a second region greater than twice the sidewall spacer thickness, a sidewall spacer formed on the sidewall of the upper conductive layer, and a contact hole positioned in the second region and self-aligned to the sidewall spacer.

따라서, 콘택홀을 형성하기 위한 별도의 사진공정 및 마스크가 필요없으며, 배선층에 콘택홀 형성을 위한 층간절연층을형성하지 않으므로, 단차를 줄일 수 있으며, 콘택홀을 채우는 물질의 후속 패터닝시 발생하는 노광 등의 문제를 해결할수 있는 잇점이 있다.Therefore, a separate photo process and a mask for forming contact holes are not required, and an interlayer insulating layer for forming contact holes is not formed in the wiring layer, thereby reducing the step difference and occurring during subsequent patterning of the material filling the contact holes. There is an advantage that can solve problems such as exposure.

Description

반도체장치의 다층 배선구조 및 그 형성방법Multilayer wiring structure of semiconductor device and method of forming the same

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 다층 배선을 형성하기 위한 레이아웃도이다, 제2A도 내지 제2E도는 종래의 다층 배선을 형성하는 방법을 설명하기 위한 단면도들이다, 제3도는 본 발명에 의한 다층 배선을 형성하기 위한 레이아웃도이다, 제4A도 및 제4B도는 상기 레이아웃도에 의해 형성된 다층 배선구조를 도시한 단면도이다, 제5A도 내지 제5B도는 상기 제4도의 본 발명에 의한 다층 배선을 형성하는 방법을 설명하기 위한 단면도들이다.FIG. 1 is a layout diagram for forming a conventional multilayer wiring. FIGS. 2A to 2E are cross-sectional views for explaining a method for forming a conventional multilayer wiring. FIG. 3 is a diagram for forming a multilayer wiring according to the present invention. 4A and 4B are sectional views showing the multilayer wiring structure formed by the layout diagram. FIGS. 5A to 5B illustrate a method of forming a multilayer wiring according to the present invention of FIG. These are cross-sectional views.

Claims (5)

반도체기판 상에 형성된 하부 도전층; 상기 하부 도전층 상에 형성된 절연층; 상기 절연층 상에 형성되어있으며, 그 사이의 간격이 측벽 스페이서 두께의 두 배보다 작은 제1영역과, 그 사이의 간격이 측벽스페이서 두께의 두배보다 큰 제2영역을 갖는 상부 도전층; 상기 상부 도전층의 측벽에 형성된 측벽스페이서; 및 상기 제2영역에 위치하고,상기 측벽 스페이서에 자기정합된 콘택홀을 구비하는 것을 특징으로 하는 반도체장치의 다층 배선구조.A lower conductive layer formed on the semiconductor substrate; An insulating layer formed on the lower conductive layer; An upper conductive layer formed on the insulating layer, the upper conductive layer having a first region having a gap therebetween being less than twice the thickness of the sidewall spacers and a second region having a gap therebetween being greater than twice the thickness of the sidewall spacers; Sidewall spacers formed on sidewalls of the upper conductive layer; And a contact hole disposed in the second region, the contact hole being self-aligned to the sidewall spacers. 반도체기판 상에 하부 도전층, 절연층, 상부 도전층을 차례로 형성하는 공정; 콘택홀이 형성될 영역의 상부 도전층의 간격이 스페이서 두께의 두배보다 크고, 콘택홀이 형성되지 않을 영역의 상부 도전층의 간격이 스페이서 두께의 두 배보다 작도록 상기 상부 도전층을 이방성 식각하는 공정; 결과물 전면에 스페이서용 물질을 도포한 후 이방성식각 함으로써 상기 상부 도전층의 측벽에 스페이서를 형성하는 공정; 및 상기 절연층을 이방성 식각함으로써 하부 도전층상에 콘택홀을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체장치의 다층 배선 형성방법.Forming a lower conductive layer, an insulating layer, and an upper conductive layer in sequence on the semiconductor substrate; Anisotropically etching the upper conductive layer such that the gap between the upper conductive layer in the region where the contact hole is to be formed is greater than twice the thickness of the spacer and the gap between the upper conductive layer in the region where the contact hole is not formed is less than twice the thickness of the spacer. fair; Forming a spacer on the sidewall of the upper conductive layer by applying an spacer material on the entire surface of the resultant and then anisotropically etching the same; And forming a contact hole on the lower conductive layer by anisotropically etching the insulating layer. 제2항에 있어서, 상기 스페이서는 상기 상부 도전층 및 절연층을 구성하는 물질과는 소정의 식각공정에 대해 식각율이 다른 물질로 구성되는 것을 특징으로 하는 반도체장치의 다층 배선 형성방법.The method of claim 2, wherein the spacer is made of a material having an etch rate different from a material forming the upper conductive layer and the insulating layer for a predetermined etching process. 제3항에 있어서, 상기 절연층은 산화물로 형성되고, 상기 스페이서는 실리콘질화막 또는 산화알루미늄으로형성되는 것을 특징으로 하는 반도체장치의 다층 배선 형성방법.4. The method of claim 3, wherein the insulating layer is formed of an oxide, and the spacer is formed of a silicon nitride film or aluminum oxide. 제2항에 있어서, 상기 상부 도전층 상에 캐핑층을 형성하는 공정을 더 구비하는 것을 특징으로 하는 반도체장치의 다층 배선 형성방법.3. The method of claim 2, further comprising forming a capping layer on the upper conductive layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950017157A 1995-06-23 1995-06-23 Multilayer interconnection structure of semiconductor apparatus and forming method thereof KR0155834B1 (en)

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KR1019950017157A KR0155834B1 (en) 1995-06-23 1995-06-23 Multilayer interconnection structure of semiconductor apparatus and forming method thereof

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KR1019950017157A KR0155834B1 (en) 1995-06-23 1995-06-23 Multilayer interconnection structure of semiconductor apparatus and forming method thereof

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KR0155834B1 KR0155834B1 (en) 1998-12-01

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