KR970002691A - 고속 시스템에 있어서, 클럭 스큐를 최소화하고 리타임 마진을 극대화 하기 위한 장치 - Google Patents

고속 시스템에 있어서, 클럭 스큐를 최소화하고 리타임 마진을 극대화 하기 위한 장치 Download PDF

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Publication number
KR970002691A
KR970002691A KR1019960002710A KR19960002710A KR970002691A KR 970002691 A KR970002691 A KR 970002691A KR 1019960002710 A KR1019960002710 A KR 1019960002710A KR 19960002710 A KR19960002710 A KR 19960002710A KR 970002691 A KR970002691 A KR 970002691A
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KR
South Korea
Prior art keywords
retime
maximizing
margin
devices
high speed
Prior art date
Application number
KR1019960002710A
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English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed filed Critical
Publication of KR970002691A publication Critical patent/KR970002691A/ko

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
KR1019960002710A 1995-06-07 1996-02-05 고속 시스템에 있어서, 클럭 스큐를 최소화하고 리타임 마진을 극대화 하기 위한 장치 KR970002691A (ko)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US48239495A 1995-06-07 1995-06-07

Publications (1)

Publication Number Publication Date
KR970002691A true KR970002691A (ko) 1997-01-28

Family

ID=23915894

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960002710A KR970002691A (ko) 1995-06-07 1996-02-05 고속 시스템에 있어서, 클럭 스큐를 최소화하고 리타임 마진을 극대화 하기 위한 장치

Country Status (4)

Country Link
JP (1) JPH09167038A (ko)
KR (1) KR970002691A (ko)
CN (1) CN1101097C (ko)
GB (1) GB2301994B (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970076176A (ko) * 1996-05-22 1997-12-12 베일리 웨인 피 클럭 스큐에 둔감한 스캔 체인 재정렬 방법 및 그를 이용한 집적회로

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4084250A (en) * 1976-09-27 1978-04-11 Honeywell Information Systems Inc. Modular assembly for an electronic computer
JPS6228823A (ja) * 1985-07-31 1987-02-06 Toshiba Corp 信号切換回路
US4744076A (en) * 1986-08-06 1988-05-10 E. I. Du Pont De Nemours And Company Bus structure having constant electrical characteristics
JPH0371798A (ja) * 1989-08-11 1991-03-27 Hitachi Ltd 車載用再生装置
US5109168A (en) * 1991-02-27 1992-04-28 Sun Microsystems, Inc. Method and apparatus for the design and optimization of a balanced tree for clock distribution in computer integrated circuits
JPH04344511A (ja) * 1991-05-22 1992-12-01 Nec Commun Syst Ltd 活線挿抜方式
DE4345604B3 (de) * 1992-03-06 2012-07-12 Rambus Inc. Vorrichtung zur Kommunikation mit einem DRAM
US5446410A (en) * 1992-04-20 1995-08-29 Matsushita Electric Industrial Co.,Ltd. Semiconductor integrated circuit
JPH06274253A (ja) * 1993-03-24 1994-09-30 Matsushita Electric Ind Co Ltd ラック装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970076176A (ko) * 1996-05-22 1997-12-12 베일리 웨인 피 클럭 스큐에 둔감한 스캔 체인 재정렬 방법 및 그를 이용한 집적회로

Also Published As

Publication number Publication date
CN1101097C (zh) 2003-02-05
GB2301994A (en) 1996-12-18
CN1149238A (zh) 1997-05-07
GB9610706D0 (en) 1996-07-31
GB2301994B (en) 1997-08-06
JPH09167038A (ja) 1997-06-24

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