GB2301994A

GB2301994A - Apparatus for minimizing clock skew in data transfer

Info

Publication number: GB2301994A
Application number: GB9610706A
Authority: GB
Inventors: Brian D Alleyne; Jae-Won Lee; Jun-Gyu Lee; Sung-Min Song; Gyu-Suk Lee
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1995-06-07
Filing date: 1996-05-22
Publication date: 1996-12-18
Anticipated expiration: 2016-05-22
Also published as: JPH09167038A; CN1149238A; GB2301994B; GB9610706D0; CN1101097C; KR970002691A

Abstract

A system having a printed circuit motherboard 39 and a plurality of printed circuit daughter boards 32,34,36,38,21-29 connected to the motherboard is disclosed. Data lines between the motherboard and between each of the daughter boards are about 9-18 inches long. Clock lines 33 between the motherboard and each of the daughter boards have a length of about 25.5 inches to about 34.5 inches. Drivers 37 and receivers 47,51 on each of the daughter boards are disposed on an edge of the board in communication with drivers 31a,31b on the motherboard. The clock lines and data lines are point-to-point connections between the motherboard and each of the daughter boards. There is a built-in serial termination resistor R at the output driver 31a,31b,37 of each of the clock and data lines. Applications are to ATM, X25, frame relay, B-ISDN or SONET.

Description

APPARATUS FOR MINIMIZING CLOCK SKEW The present invention generally relates to high speed systems having many data and clock lines, and, more particularly, to an apparatus for minimizing clock skew and maximizing the retime margin using one system clock.

Clock signals provide for timing and control of data transfers between components on a system. Whist designers seek the shortest data/clock lines to achieve the highest transfer speeds, as the complexity of the system components increases, the number of signal path interconnections and the length of the signal paths increase, and the data/clock lines of the clock unit must be lengthened accordingly. In addition to reduced system speeds, increasing the length of the data/clock lines causes problems with clock skew as well as increasing the likelihood of a loss of signal integrity.

In order to reduce signal loss along a data path in a high speed system, some have tried to design slower, but multiple, data path lines so as not to sacrifice bandwidth or throughput. Multiple data lines, however, increases the likelihood of signal loss at the receiver.

Others have tried to reduce the length of the signal lines by matching the propagation delay of the high speed data path to transmission line impedance. This technique is hard to achieve as there are many differing line lengths and thus impedances - that must be considered, and distortion inevitably results from mismatched impedances.

In light of the foregoing, there exists a need for an apparatus that maintains high data transfer speeds while minimizing clock skew and maximising retime margins at the receiver.

The present invention is directed to a printed circuit board arrangements for a system incorporating data and clock lines, which substantially obviates one or more of the problems due to the limitations and disadvantages of the related art.

Accordingly, the present invention provides a system having a printed circuit mother board and a plurality of printer circuit daughter boards connected to said mother board, comprising: data lines between said mother board and each of the said daughter boards having a length of about 9 inches to about 18 inches; and clock lines between said mother board and each of the said daughter boards having a length of about 25.5 inches to about 34.5 inches.

Preferably, the system further includes a driver and a receiver on each of the said plurality of daughter boards, coupled to respective ends of the data lines, the drivers and receivers being disposed on the edges of the daughter boards. The set-up and hold times of the drivers and receivers may be about 1.5 nanoseconds and zero nanoseconds respectively. The propagation delay between the drivers and receivers may be about 2.4 to about 7.0 nanoseconds.

Preferably, the system further includes a plurality of clock units, each of the said plurality of clock units having a driver and a receiver, coupled to respective ends of the clock lines, the drivers and receivers being disposed on the edges of the clock units.

The clock and data lines preferably have point-to-point connections between the mother board and each of the daughter boards.

Preferably, the system further includes a built-in serial termination resistor at an output driver of each of the clock and data lines. The resistor may have a value of approximately 47 ohms.

The data and clock lines preferably have an impedance of about 60 ohms.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which: Figure 1 is a diagrammatical representation of the system structure operable with the present invention; Figure 2 is a schematic representation of a system having one mother board and thirteen daughter boards; Figure 3 is a rear view of the mother board of Figure 2 with the male connectors for the daughter boards illustrated; Figure 4 is an exploded perspective view of the point-topoint clock line connections in accordance with the present invention; Figure 5 is a circuit diagram illustrating the clock lines of the present invention; Figure 6A is an exploded perspective view of the point-topoint data line connections for six of the daughter boards of the present invention;; Figure 6B is an exploded perspective view of the point-topoint data line connections for the remaining daughter boards of the present invention; Figure 7 is a schematic diagram of the point-to-point data line connections in accordance with the present invention; and Figure 8 is a circuit diagram illustrating the data lines of the present invention.

Referring now to the drawings, and more particularly to Figure 1, there is shown a general overview of a system architecture 10 employing the apparatus of the present invention. While the invention is described with respect of a bus architecture for illustrative purposes, it is understood that the teachings of the present invention may be practised when using any high speed data systems, for example, high speed telecommunications systems.

As shown, the system bus architecture includes a backplane bus 12 in communication with a plurality of, respectively, system processor units (SPU) 14a and 14b, system interface units (SIU) 16, system switch units (SSU) 18, and system clock units (SCU) 20. While there are plurality of SPUs, SIUs, SSUs and SCUs shown in Figure 1, it is understood that depending on the particular system configuration, any number of the respective units may interface with the backplane 12, including single embodiments of the respective units.

In the embodiment shown, the backplane bus 12 supports communication between an active SPU 14a on the master side, and the various interface 16, switch 18 and clock 20 units on the slave side. The standby SPU 14b also runs in the slave mode. Either one, but only one, of the SPUs may be designated the master (active), and the other must be designated a slave (standby) as there can be only one master processor for the system.

The present invention will be described with reference to an embodiment comprising a motherboard with a clock board 39 (SCU), containing two SCUs 30a and 30b (hot/standby), interfacing with thirteen daughter boards as represented in Figure 2. The thirteen daughter boards consist of two SSUs 32 and 34 (for 1:1 redundancy), two SPUs 36 and 38, and nine SIUs 21-29.

As shown in Figure 2, a plurality of 50MHz clock lines 33 (using Pseudo Emitter Coupled Login (PECL) signals) are generated from clock drivers 31a and 31b and are received at each of the respective daughter boards.

In addition, a plurality of 50Mbps (million bits per second) data lines 35 (Transistor-Transistor Logic; TTL signals) connect the two SSUs 32 and 34 with the nine SIUs 21-29 and two SPUs 36 and 38. As shown in Figure 2, data flow is bidirectional.

Each of the clock drivers 31a and 31b and data drivers 37 contain a built-in serial termination resistor R at the immediate output of the driver. The R value is approximately 470hms. It is understood that the resistor value may vary within the practice of the invention.

Also, while the resistor R may be placed somewhere downstream of the driver output, it is advantageous to position the resistor R at the output of the drivers since this has the greatest effect on reducing signal distortion.

Figure 3 illustrates the rear view of the mother board of Figure 2 with the daughter board connection arrangement depicted. Each of the daughter boards is connected using a male connector, for example, an AMP Z-PACK 2mm HM connector. Other suitable and equivalent connections may be used.

Figure 4 depicts an exploded perspective vie of the 50MHz clock line connections between the clock units 30a and 30b, and the daughter boards. Each daughter board receives a +SOMHz and a -50MHz clock sign from each of the two SCUs 30a and 30b. Accordingly, four clock lines per daughter board are supported, with a total signal trace of 52 lines.

As clearly seen in Figure 4, the clock line connections between the daughter boards and the SCUs are point-to-point connections.

A representative circuit level diagram of the clock unit 30a/daughter board interface is shown in Figure 5. It is understood that each of the clock unit/daughter board connections contains similar circuitry. As illustrated, clock driver 31a generates a +50MHz and -50MHz PECL clock signal that is connected to a daughter board receiver 51, via a clock line 33 with an approximate length of 30 inches (+/- 15%).

Also shown are resistors R, with a value of 47 ohms, coupled at the output of the driver 31a to reduce signal distortion. Further, the driver and receiver are located at the edges of the boards to minimize the signal path cm of the edge of the respective boards. It is understood that some variation in dimensions is possible within the practice of this invention. ZO for the 50MHz clock lines is 600hms (+/- 15%) The data lines 35 of the present invention will now be described in greater detail. The data lines are connected to exchange asynchronous transfer mode (ATM) cells. Each ATM cell is 53 bytes in length, consisting of a 5 byte header field and a 48 byte information field.

The data lines, however, can also carry other traditional packet topologies (eg X25 or frame relay) and is generally capable of carrying any high speed telecommunications information, such as B-ISDN (Broadband Integrated Services Digital Network) or SONET (synchronous optical network).

Referring to Figures 6A and 6B, there is illustrated the bidirectional point-to-point data line connections between the SSUs 32 and 34, and the other eleven daughter boards.

As discussed above, the data lines use TTL signals.

As shown in Figure 6A, twelve (12) data lines connect the SSUs 32 and 34 with the SPUs 36 and 38. Forty two (42) data lines connect each of the SSUs 32 and 34 with the respective SIUs 21-24. In Figure 6B, twelve (12) data lines connect each of the SSUs 32 and 34 with SIUs 28 and 29, and forty two (42) data lines connect each of the SSUs 32 and 34 with the respective SIUs 25-27. Combined, Figures 6A and 6B contain 330 data traces.

Figure 7 illustrates that the length of the data lines is approximately 9-18 inches, as measured from the SSUs 32 and 34 to the remaining eleven daughter boards. Figure 8 is a circuit level diagram of the connections illustrated in Figures 6A, 6B and 7, depicting the respective data drivers 37 and data receivers 47. Resistor R (47 ohms) is disposed at the output of the drivers 37 to reduce signal distortion as discussed previously with regard to the clock drivers.

As shown in Figure 8, the data signals from the each SIU and SPU is sent to each SSU respectively, for 1:1 redundancy. Also, for redundancy reasons, each of the SSUs sends a data signal to each respective SIU or SPU. As illustrated, the data line length is about 9-18 inches with a 2.4-7.0 nanosecond propagation delay between the data driver and the receiver, allowing retiming of the data without loss at the receiver. ZO for the 50Mbps data paths is 60 ohms (+/- 15%). The set-up and hold times of the drivers/receivers on the daughter boards are about 1.5 nanoseconds and zero nanoseconds, respectively.

In addition, as shown in Figure 8, the data drivers 37 and receivers 47 are disposed within 0.5-2.0 inches of the edge of the respective boards. The exact dimensions may vary in the practice of the invention.

In summary, the present invention provides many advantages.

The clock paths utilize point-to-point connections which minimizes clock skew and distortion of the clock signal.

Clock skew is also minimized since the lengths of each clock path are approximately equal.

The data lines also utilize point-to-point connections.

The length of the data lines is kept within about 9 to 18 inches to minimize propagation delay while allowing retiming of the data at the receiver without loss. Having data lines of uniform length and clock lines of uniform length, combined with positioning the drivers/receivers on the daughter boards in a propagation delay of the driver, set-up/hold time, and clock rise/fall times.

Moreover, a uniform characteristic impedance of about 60 ohms for the data/clock signals on the daughter/mother boards is matched to the impedance of the inter-board connector pin, thereby reducing distortion due to mismatched impedances.

To further reduce signal distortion, serial resistors are attached on the output side of the transmitting drivers.

In addition, 50 Mbps data exchange can take place over the mother board within one cycle of the 50MHz clock.

While the invention has been described in terms of the embodiments described above, those skilled in the art will recognize that the invention can be practised with modification within the spirit and scope of the appended claims.

Claims

CLAIMS:

1. A system having a printed circuit mother board and a plurality of printer circuit daughter boards connected to said mother board, comprising: data lines between said mother board and each of the said daughter boards having a length of about 9 inches to about 18 inches; and clock lines between said mother board and each of the said daughter boards having a length of about 25.5 inches to about 34.5 inches.

2. A system according to claim 1, further including a driver and a receiver on each of the said plurality of daughter boards, coupled to respective ends of the data lines, the drivers and receivers being disposed on the edges of the daughter boards.

3. A system according to claim 2 in which the set-up and hold times of the drivers and receivers are about 1.5 nanoseconds and zero nanoseconds respectively.

4. A system according to claim 2 or claim 3 in which the propagation delay between the drivers and receivers is about 2.4 to about 7.0 nanoseconds.

5. A system according to any preceding claim, further including a plurality of clock units, each of the said plurality of clock units having a driver and a receiver, coupled to respective ends of the clock lines, the drivers and receivers being disposed on the edges of the clock units.

6. A system according to any preceding claim in which the clock lines have point-to-point connections between the mother board and each of the daughter boards.

7. A system according to any preceding claim in which the data lines have point-to-point connections between the mother board and each of the daughter boards.

8. A system according to any preceding claim, further including a built-in serial termination resistor at an output driver of each of the clock and data lines.

9. A system according to claim 8 in which the resistor has a value of approximately 47 ohms.

10. A system according to any preceding claim in which the data and clock lines have an impedance of about 60 ohms.

11. A system having a printed circuit mother board and a plurality of printer circuit daughter boards connected to said mother board, substantially as described herein with reference to the accompanying drawings.