CN1149238A

CN1149238A - Apparatus for minimizing clock skew and maximizing retime margin in high speed system

Info

Publication number: CN1149238A
Application number: CN96106839A
Authority: CN
Inventors: B·D·阿利恩; J·W·李; J·G·李; S·M·宋; G·S·李
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1995-06-07
Filing date: 1996-06-04
Publication date: 1997-05-07
Anticipated expiration: 2016-06-04
Also published as: CN1101097C; JPH09167038A; GB2301994A; GB9610706D0; KR970002691A; GB2301994B

Abstract

A system having a printed circuit motherboard 39 and a plurality of printed circuit daughter boards connected to the motherboard is disclosed. Data lines between the motherboard and between each of the daughter boards are about 9-18 inches long. Clock lines between the motherboard and each of the daughter boards have a length of about 25.5 inches to about 34.5 inches. Drivers and receivers on each of the daughter boards are disposed on an edge of the board in communication with drivers on the motherboard. The clock lines and data lines are point-to-point connections between the motherboard and each of the daughter boards. There is a built-in serial termination resistor at the output driver of each of the clock and data lines.

Description

Clock skew is minimized and the maximized device of the scope of retiming

The present invention relates generally to have the High Speed System of a lot of data and clock line, specifically, relate to and utilize a system clock, clock skew is minimized and make the maximized device of the scope of retiming.

Clock signal provides regularly and control for the transfer of data between the parts in a system.Though the designer seeks the shortest data/clock line, to obtain the highest transmission speed, but, make the number and the signal path lengths of signal path interconnection also increase, and then also make the data/clock line of clock unit correspondingly extend along with the increase of system unit complexity.Except that the speed that has reduced system, the data/increase of clock line length also causes the problem of clock skew, and has increased the possibility of loss signal integrality.

In order to reduce in the High Speed System loss of signal along data path, some technical staff is attempting design than low speed but be multiple data path line, so that not sacrificial property bandwidth or information throughput.But the multiple data line has strengthened the possibility of the receiver aspect loss of signal.

Other people attempt to mate with transmission line impedance by the propagation delay that makes high speed data path, reduce the length of holding wire.Owing to many different line lengths are arranged, thereby have many different impedances (they must be considered), these unmatched impedances will inevitably cause distortion, this technology also is difficult to realize.

In view of the foregoing, need a kind ofly can when keeping high speed data transfer, make the clock skew of receiving terminal minimize and make the maximized apparatus and method of the scope of retiming.

The object of the present invention is to provide a kind of PCB design that is used to contain the system of data and clock line, it can be eliminated basically because the limitation of prior art and one or more problems that defective causes.

Generally speaking, when the design system motherboard, the length of data wire should remain between the 9-18 inch, extends with the propagation of satisfying between data driver and the receiver.The length of all clock lines should be consistent basically, is approximately 30 inches (± 15%).

The driver of all clock lines and data wire and receiver all are arranged on the daughter board edge with the motherboard interfaces, to reduce the length of line.And the starting/retention time of driver and receiver all remains the shortest.

All clock lines all are designed to point-to-point the connection with data wire, and this has reduced the delay of signal when a burst is provided.In output end of driver, all data wires and clock line all have establishes series terminal resistance in one, in order to reduce signal distortion.

According to the present invention, in order to obtain these and other advantage, property and sensu lato description as an example, the invention provides a system with a printed circuit mother board and a plurality of connected printed circuit subboards, comprise the data wire between motherboard and each daughter board, their length is about 9 inches to 18 inches, and the clock line between motherboard and each daughter board, and its length is about 25.5 inches to 34.5 inches.

Should be appreciated that above general introduction and follow-up detailed description are illustrative and indicative, are intended to the further instruction that the invention provides that limits for claims.

Below in conjunction with accompanying drawing preferred embodiment of the present invention is described in detail, so that understand above and other objects of the present invention, characteristics and advantage better.In the drawings:

Fig. 1 is the schematic diagram that can utilize the system configuration of work of the present invention;

Fig. 2 is the schematic diagram that has the system of a motherboard and 13 daughter boards;

Fig. 3 is the rearview of motherboard among Fig. 2, have provide shown in the male connector used of each daughter board;

Fig. 4 is the exploded view that point-to-point clock line connects according to the present invention;

Fig. 5 is the circuit diagram of expression clock line of the present invention;

Fig. 6 A is the exploded view that is used for the Point-to-Point Data line connection of 6 daughter boards of the present invention;

Fig. 6 B is the exploded view that is used for the Point-to-Point Data line connection of other daughter board of the present invention;

Fig. 7 is the structural representation that connects according to Point-to-Point Data line of the present invention; And

Fig. 8 is the circuit diagram of data wire of the present invention.

Referring now to accompanying drawing,, particularly referring to Fig. 1, it illustrates a full view that has adopted the system architecture 10 of apparatus of the present invention.Although for convenience of explanation, the present invention describes with a relative bus architecture, it should be understood that, is using any high-speed data system, for example during some high-speed telecommunication systems, can both use technology of the present invention.

As shown in the figure, system bus architecture comprises a backplane bus 12, and it communicates with a plurality of system processors unit (SPU) 14a and 14b, system interface unit (SIU) 16, systems exchange unit (SSU) 18 and system clock unit (SCU) 20 respectively.Though a plurality of SPU, SIU, SSU and SCU shown in Fig. 1 should be understood that according to concrete system configuration, each unit of arbitrary number comprises the isolated system of these unit, can with backplane bus 12 interfaces.

In illustrated embodiment, backplane bus 12 is supported one of the main equipment sides communication between each interface unit 16, crosspoint 18 and the clock unit 20 of now using SPU14a and slave side.Standby SPU14b is also with the subordinate mode operation.Among the SPU any one (but can only be one) can be designated as master's (existing using) equipment, and other subordinate (standby) equipment that then all is designated as because for a system, can only have a primary processor.

Describe the present invention below in conjunction with an embodiment, in this embodiment, comprise a motherboard that has a clock board 39 (SCU), clock board 39 contains two SCU30a and 30b (mainboard/standby plate), and with 13 daughter board interfaces, as shown in Figure 2.These 13 daughter boards are made up of two SSU32 and 34 (being used for 1: 1 redundancy), two SPU36 and 38 and 9 SIU21-29.

As shown in Figure 2, many 50MHz clock lines 33 (adopting pseudo-emitter coupled logic (PECL) signal) produce from

clock driver

31a and 31b, and are each daughter board reception.

In addition, many 50Mbps (megabits per second) data wire 35 (transistor-transistor logics; The TTL signal) two SSU32 and 34 is connected with two SPU36 and 38 with 9 SIU21-29.As shown in the figure, data are mobile is two-way.

Each

clock driver

31a and 31b and data driver 37 contain the series terminal resistance R of establishing at the direct output of this driver, and its value is approximately 47 ohm.Will of course be appreciated that this resistance value can change in practical application of the present invention.

And though this resistance R can be arranged on the somewhere, downstream of driver output, it is best that resistance R is arranged on output end of driver, because can reduce the distortion of signal so most effectively.

Fig. 3 illustrates the rearview of motherboard among Fig. 2, and has indicated the connected mode of daughter board.Each daughter board is by a male connector, and for example AMP Z-PACK 2mm HM connector connects.Certainly can also adopt some other to be suitable for and equivalent connector.

Fig. 4 shows the exploded view that is connected with 50MHz clock line between each daughter board at clock unit 30a and 30b.Each daughter board receive among two SCU30a and the 30b each+50MHz and-the 50MHz clock signal.Correspondingly, each daughter board support has four clock lines, and the resultant signal track is 52 lines.As clear illustrating among Fig. 4, it is point-to-point connection that each daughter board is connected with clock line between the SCU.

Fig. 5 shows the circuit level figure of clock unit 30a/ daughter board interface.Be to be understood that each clock unit/daughter board connects and all contains similar circuit.As shown in the figure, clock driver 31a produce one+50MHz and-50MHz PECL clock signal, this signal is about the clock line 33 of 30 inches (± 15%) through a length, is connected to a daughter board receiver 51.

Resistance R also is shown among the figure, and its value is 47 ohm, is coupling in the output of driver 31a, to reduce signal distortion.And driver and receiver all are positioned at the edge of these plates, so that the signal path lengths minimum.As shown in the figure, driver and receiver are arranged in the about 1.3-3.0cm of each panel edges.Be to be understood that in practical application of the present invention, some variation of size aspect also is possible.The ZO of 50MHz clock line is 60 ohm (± 15%).

Data wire 35 of the present invention is described now in more detail.Connect data wire, with exchange ATM(Asynchronous Transfer Mode) unit.Each atm cell length is 53 bytes, is made of the header field of 5 bytes and the information field of 48 bytes.

But data wire also can carry some other conventional data packet topological structure (for example X.25 or frame delay), and can carry any high speed telecom information usually, such as B-ISDN (broadband integrated service digital network) or SONET (Synchronous Optical Network) etc.

Referring to Fig. 6 A and 6B, they show SSU32 and 34 with other 11 daughter boards between two-way Point-to-Point Data line be connected.As discussed above, these data wires adopt the TTL signal.

As shown in Figure 6A, 12 data wires with SSU32 and 34 and SPU36 and 38 couple together.Article 42, data wire couples together each SSU32 and 34 with corresponding SIU21-24.In Fig. 6 B, 12 data wires with each SSU32 and 34 and SIU28 and 29 couple together, and 42 data wires couple together each SSU32 and 34 with corresponding SIU25-27.Altogether, Fig. 6 A and 6B comprise 330 data track.

Fig. 7 illustrates from SSU32 and 34 and measures to all the other 11 daughter boards, and the length of its data wire is roughly the 9-18 inch.Fig. 8 is Fig. 6 A, 6B and the circuit level figure that is connected shown in 7, wherein shows corresponding data driver 37 and data sink 47.As the discussion that the front is done about clock driver, resistance R (47 ohm) is arranged on the output of driver 37, in order to reduce signal distortion.

As shown in Figure 8, send to each SSU from the data-signal of each SIU and SPU respectively with 1: 1 redundancy.And because redundant, each SSU sends to each self-corresponding SIU or SPU with a data-signal.As shown in the figure, data wire length is approximately the 9-18 inch, and the propagation delay of 2.4-7.0 nanosecond is arranged between data driver and the receiver, loses in the receiver end no signal to allow retiming of data.The ZO of 50Mbps data path is 60 ohm (± 15%).The foundation of driver and retention time are approximately 1.5 nanoseconds and 0 nanosecond respectively on these daughter boards.

In addition, as shown in Figure 8, data driver 37 and receiver 47 are arranged in the 0.5-2.0 inch scope of each panel edges.In practical application of the present invention, actual size can change.

In a word, the present invention has many advantages.Clock path utilizes point-to-point connection, makes the distortion of clock skew and clock signal can reduce to minimum.Because the length of each clock path about equally, thereby also make the clock skew minimum.

Data wire also adopts point-to-point connection.Data wire length remains within about 9 to 18 inches, although so that propagation delay reduces, make the no signal loss of retiming of the data of receiver end simultaneously.Have the data wire of even length and the clock line of even length, and in even mode driver is set on daughter board, the two in conjunction with make to clock skew, pattern postpone, the propagation delay of driver, foundation/retention time and the influence of clock risings/fall time reduce to minimum.

In addition, make data/clock signal on son/motherboard be approximately the impedance phase coupling of connector pin between 60 ohm uniform properties impedance and plate, thereby reduced because the distortion that impedance mismatching causes.

In order further to reduce signal distortion, in the output adjunction of transmit driver series resistance.In addition, within the one-period of 50MHz clock, on whole motherboard, can carry out the exchanges data of 50Mbps.

Though more than be that invention has been described in conjunction with the embodiments, those skilled in the art will be understood that, within the spirit and scope of appended claims, also can implement the present invention by the mode of revising.

Claims

1. system with a printed circuit mother board and a plurality of printed circuit subboards that are attached thereto is characterized in that comprising:

Data wire between described motherboard and each the described daughter board, its length are about 9 inches to 18 inches; With

Clock line between described motherboard and each the described daughter board, its length are about 25.5 inches to 34.5 inches.

2. system as claimed in claim 1 is characterized in that, also being included on each of described a plurality of daughter boards all has driver and receiver, and the respective end with described data wire is coupled respectively; Described driver and receiver are arranged on the edge of described daughter board.

3. system as claimed in claim 2 is characterized in that, the settling time of described driver and receiver and retention time are respectively about 1.5 nanoseconds and 0 nanosecond.

4. system as claimed in claim 1, it is characterized in that, also comprise a plurality of clock units, each of described a plurality of clock units all has driver and the receiver with the coupling of the respective end of described clock line, and described driver and receiver are arranged on the edge of described clock unit.

5. system as claimed in claim 1 is characterized in that, between described motherboard and each described daughter board, described clock line has point-to-point connection.

6. system as claimed in claim 1 is characterized in that, between described motherboard and each described daughter board, described data wire has point-to-point connection.

7. system as claimed in claim 1 is characterized in that, also is included on the output driver of each described clock line and data wire and establishes series terminal resistance.

8. system as claimed in claim 7 is characterized in that, the resistance of described resistance is about 47 ohm.

9. system as claimed in claim 1 is characterized in that, the impedance of described data wire and clock line is about 60 ohm.

10. system as claimed in claim 2 is characterized in that, the propagation delay between described driver and the receiver is about 2.4 to 7.0 nanoseconds.