KR960039372A - Capacitor of semiconductor device and manufacturing method thereof - Google Patents

Capacitor of semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR960039372A
KR960039372A KR1019950009447A KR19950009447A KR960039372A KR 960039372 A KR960039372 A KR 960039372A KR 1019950009447 A KR1019950009447 A KR 1019950009447A KR 19950009447 A KR19950009447 A KR 19950009447A KR 960039372 A KR960039372 A KR 960039372A
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South Korea
Prior art keywords
conductive layer
lower electrode
layer
contact hole
semiconductor device
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KR1019950009447A
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Korean (ko)
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권기원
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김광호
삼성전자 주식회사
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Priority to KR1019950009447A priority Critical patent/KR960039372A/en
Publication of KR960039372A publication Critical patent/KR960039372A/en

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Abstract

실리사이드층의 응집현상을 이용하여 하부전극의 표면적을 넓히는 반도체 장치의 커패시터 및 그 제조방법에 관하여 개시한다. 본 발명은 하부전극, 유전막 및 상부전극으로 이루어지는 반도체 장치의 커패시터에 있어서, 반도체 기판 상에 콘택홀을 갖는 절연막과, 상기 콘택홀을 통해 상기 기판에 접속되는 도전층과, 상기 도전층의 표면에 요철을 갖는 실리사이드층을 구비하며, 상기 도전층 및 실리사이드층으로 상기 하부전극을 구성한다. 본 발명에 의하면, 실리사이드의 응집현상을 이용하여 공정을 용이하게 하부전극의 표면적을 넓혀 정전용량이 증가된 커패시터를 얻을 수 있다.Disclosed are a capacitor of a semiconductor device and a method of manufacturing the same, which widen the surface area of a lower electrode by using cohesion of a silicide layer. A semiconductor device capacitor comprising a lower electrode, a dielectric film, and an upper electrode, comprising: an insulating film having a contact hole on a semiconductor substrate, a conductive layer connected to the substrate through the contact hole, and a surface of the conductive layer. A silicide layer having irregularities is provided, and the lower electrode is formed of the conductive layer and the silicide layer. According to the present invention, it is possible to obtain a capacitor having an increased capacitance by widening the surface area of the lower electrode by using the coagulation phenomenon of silicide.

Description

반도체 장치의 커패시터 및 그 제조방법Capacitor of semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도 내지 제5도는 본 발명에 의한 제1 실시예의 커패시터 제조방법을 공정순서대로 도시한 단면도들이다.1 to 5 are cross-sectional views showing the capacitor manufacturing method of the first embodiment according to the present invention in the process order.

Claims (6)

하부전극, 유전막 및 상부전극으로 이루어지는 반도체 장치의 커패시터에 있어서, 반도체 기판 상에 콘택홀을 갖는 절연막; 상기 콘택홀을 통해 상기 기판에 접속되는 도전층; 및 상기 도전층의 표면에 요철을 갖는 실리사이드층을 구비하며, 상기 도전층 및 실리사이드층으로 상기 하부전극을 구성하는 것을 특징으로 하는 반도체 장치의 커패시터.A capacitor of a semiconductor device comprising a lower electrode, a dielectric film, and an upper electrode, comprising: an insulating film having a contact hole on a semiconductor substrate; A conductive layer connected to the substrate through the contact hole; And a silicide layer having irregularities on the surface of the conductive layer, wherein the lower electrode comprises the conductive layer and the silicide layer. 하부전극, 유전막 및 상부전극으로 이루어지는 반도체 장치의 커패시터에 있어서, 반도체 기판 상에 콘택홀을 갖는 절연막; 및 상기 콘택홀을 통해 상기 기판에 접속되고, 그 표면에 요철을 갖는 도전층을 구비하며, 상기 도전층으로 상기 하부전극을 구성하는 것을 특징으로 하는 반도체 장치의 커패시터.A capacitor of a semiconductor device comprising a lower electrode, a dielectric film, and an upper electrode, comprising: an insulating film having a contact hole on a semiconductor substrate; And a conductive layer connected to the substrate through the contact hole and having irregularities on the surface thereof, wherein the lower electrode is constituted by the conductive layer. 하부전극, 유전막 및 상부전극으로 이루어지는 반도체 장치의 커패시터 제조방법에 있어서, 반도체 기판상에 콘택홀을 갖는 절연막을 형성하는 단계; 상기 콘택홀을 통해 상기 기판에 접속되는 도전층을 형성하는 단계; 상기 도전층의 표면에 전이금속층을 형성하는 단계; 및 상기 도전층과 전이금속층을 반응시켜 상기 도전층의 표면에 요철을 갖는 실리사이드층을 형성하여 상기 하부전극으로 상기 도전층 및 실리사이드층을 이용하는 것을 특징으로 하는 반도체 장치의 커패시터 제조방법.A capacitor manufacturing method of a semiconductor device comprising a lower electrode, a dielectric film and an upper electrode, the method comprising: forming an insulating film having a contact hole on a semiconductor substrate; Forming a conductive layer connected to the substrate through the contact hole; Forming a transition metal layer on a surface of the conductive layer; And forming a silicide layer having irregularities on the surface of the conductive layer by reacting the conductive layer and the transition metal layer to use the conductive layer and the silicide layer as the lower electrode. 제3항에 있어서, 상기 천이금속층은 Ti, Mo, Pt, W, Ta, Ni, Co, Pb, Hf, Zr, V, Cr, Fe, Nb, Ru, Rh, Re, Os 및 Ir으로 이루어진 일군에서 선택된 하나를 이용하여 형성하는 것을 특징으로 하는 반도체 장치의 커패시터 제조방법.The group of claim 3, wherein the transition metal layer is formed of Ti, Mo, Pt, W, Ta, Ni, Co, Pb, Hf, Zr, V, Cr, Fe, Nb, Ru, Rh, Re, Os, and Ir. Capacitor manufacturing method of a semiconductor device, characterized in that formed using one selected from. 하부전극, 유전막 및 상부전극으로 이루어지는 반도체 장치의 커패시터 제조방법에 있어서, 반도체 기판상에 콘택홀을 갖는 절연막을 형성하는 단계; 상기 콘택홀을 통해 상기 기판에 접속되는 도전층을 형성하는 단계; 상기 도전층의 표면에 전이금속층을 형성하는 단계; 상기 도전층과 전이금속층을 반응시켜 상기 도전층의 표면에 요철을 갖는 실리사이드층을 형성하는 단계; 및 상기 표면에 요철을 갖는 실리사이드층을 제거하여, 상기 도전층의 표면에 요철을 형성하여, 상기 하부전극으로 상기 요철을 갖는 도전층을 이용하는 것을 특징으로 하는 반도체 장치의 커패시터 제조방법.A capacitor manufacturing method of a semiconductor device comprising a lower electrode, a dielectric film and an upper electrode, the method comprising: forming an insulating film having a contact hole on a semiconductor substrate; Forming a conductive layer connected to the substrate through the contact hole; Forming a transition metal layer on a surface of the conductive layer; Reacting the conductive layer with the transition metal layer to form a silicide layer having irregularities on the surface of the conductive layer; And removing the silicide layer having irregularities on the surface to form irregularities on the surface of the conductive layer and using the conductive layer having the irregularities as the lower electrode. 제5항에 있어서, 상기 실리사이드층의 제거는 불산용액을 이용하여 수행하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.The method of claim 5, wherein the silicide layer is removed using a hydrofluoric acid solution. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950009447A 1995-04-21 1995-04-21 Capacitor of semiconductor device and manufacturing method thereof KR960039372A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980016024A (en) * 1996-08-26 1998-05-25 김주용 Method for forming capacitor of semiconductor device
KR20040006499A (en) * 2002-07-12 2004-01-24 주식회사 하이닉스반도체 Method of making cell capacitor of dram and mdl device
KR100431820B1 (en) * 1999-12-28 2004-05-20 주식회사 하이닉스반도체 Manufacturing method for storage node of semiconductor device
KR100927785B1 (en) * 2002-11-20 2009-11-20 매그나칩 반도체 유한회사 Capacitor Formation Method for Semiconductor Device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980016024A (en) * 1996-08-26 1998-05-25 김주용 Method for forming capacitor of semiconductor device
KR100431820B1 (en) * 1999-12-28 2004-05-20 주식회사 하이닉스반도체 Manufacturing method for storage node of semiconductor device
KR20040006499A (en) * 2002-07-12 2004-01-24 주식회사 하이닉스반도체 Method of making cell capacitor of dram and mdl device
KR100927785B1 (en) * 2002-11-20 2009-11-20 매그나칩 반도체 유한회사 Capacitor Formation Method for Semiconductor Device

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