KR970018542A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR970018542A
KR970018542A KR1019950032962A KR19950032962A KR970018542A KR 970018542 A KR970018542 A KR 970018542A KR 1019950032962 A KR1019950032962 A KR 1019950032962A KR 19950032962 A KR19950032962 A KR 19950032962A KR 970018542 A KR970018542 A KR 970018542A
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KR
South Korea
Prior art keywords
semiconductor substrate
polysilicon layer
forming
insulating film
doped
Prior art date
Application number
KR1019950032962A
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Korean (ko)
Inventor
김현수
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950032962A priority Critical patent/KR970018542A/en
Publication of KR970018542A publication Critical patent/KR970018542A/en

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Abstract

반도체장치의 캐패시터 제조 방법이 개시되어 있다. 본 발명은 반도체 기판 상에 절연막을 형성하는 단계; 상기 절연막을 패터닝하여 상기 반도체기판의 소정영역이 노출되도록 절연막 패턴을 형성하는 단계; 상기 절연막 패턴이 형성된 반도체기판 전면에 도우핑된 폴리실리콘막을 형성하는 단계; 상기 도우핑된 폴리실리콘막을 패터닝하여 상기 반도체기판의 소정영역을 덮는 축적전극을 형성하는 단계; 상기 축적전극의 표면에 HSG 폴리실리콘층을 형성하는 단계; 상기 HSG 폴리실리콘층을 도우핑시키는 단계; 및 상기 도우핑된 HSG 폴리실리콘층이 형성된 반도체기판 전면에 유전막 및 플레이트 전극을 차례로 형성하는 단계를 포함하는 것을 특징으로 하는 반도체장치의 캐패시터 제조방법을 제공한다.A method of manufacturing a capacitor of a semiconductor device is disclosed. The present invention includes forming an insulating film on a semiconductor substrate; Patterning the insulating film to form an insulating film pattern to expose a predetermined region of the semiconductor substrate; Forming a doped polysilicon film on an entire surface of the semiconductor substrate on which the insulating film pattern is formed; Patterning the doped polysilicon layer to form an accumulation electrode covering a predetermined region of the semiconductor substrate; Forming an HSG polysilicon layer on a surface of the storage electrode; Doping the HSG polysilicon layer; And sequentially forming a dielectric film and a plate electrode on a front surface of the semiconductor substrate on which the doped HSG polysilicon layer is formed.

본 발명에 의하면, HSG 폴리실리콘층을 형성한 후 이를 도우핑시킴으로써, 균일한 불순물농도를 가지면서 표면적이 큰 축적전극을 형성할 수 있어 캐패시터의 신뢰성 및 정전용량을 크게 개선시킬 수 있다.According to the present invention, by forming and then doping the HSG polysilicon layer, it is possible to form a storage electrode having a large surface area while having a uniform impurity concentration, thereby greatly improving the reliability and capacitance of the capacitor.

Description

반도체 장치의 캐패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 의한 반도체 장치의 캐패시터 제조 방법을 설명하기 위한 단면도들이다.4 is a cross-sectional view illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.

Claims (2)

반도체 기판 상에 절연막을 형성하는 단계; 상기 절연막을 패터닝하여 상기 반도체기판의 소정영역이 노출되도록 절연막 패턴을 형성하는 단계; 상기 절연막 패턴이 형성된 반도체기판 전면에 도우핑된 폴리실리콘막을 형성하는 단계; 상기 도우핑된 폴리실리콘막을 패터닝하여 상기 반도체기판의 소정영역을 덮는 축적전극을 형성하는 단계; 상기 축적전극의 표면에 HSG 폴리실리콘층을 형성하는 단계; 상기 HSG 폴리실리콘층을 도우핑시키는 단계; 및 상기 도우핑된 HSG 폴리실리콘층이 형성된 반도체기판 전면에 유전막 및 플레이트 전극을 차례로 형성하는 단계를 포함하는 것을 특징으로 하는 반도체장치의 캐패시터 제조방법.Forming an insulating film on the semiconductor substrate; Patterning the insulating film to form an insulating film pattern to expose a predetermined region of the semiconductor substrate; Forming a doped polysilicon film on an entire surface of the semiconductor substrate on which the insulating film pattern is formed; Patterning the doped polysilicon layer to form an accumulation electrode covering a predetermined region of the semiconductor substrate; Forming an HSG polysilicon layer on a surface of the storage electrode; Doping the HSG polysilicon layer; And sequentially forming a dielectric film and a plate electrode on a front surface of the semiconductor substrate on which the doped HSG polysilicon layer is formed. 제1항에 있어서, 상기 도우핑된 HSG 폴리실리콘층은 PODl3로 도우핑시키는 것을 특징으로 하는 반도체장치의 캐패시터 제조방법.The method of claim 1, wherein the doped HSG polysilicon layer is doped with PODl3.
KR1019950032962A 1995-09-29 1995-09-29 Capacitor Manufacturing Method of Semiconductor Device KR970018542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950032962A KR970018542A (en) 1995-09-29 1995-09-29 Capacitor Manufacturing Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950032962A KR970018542A (en) 1995-09-29 1995-09-29 Capacitor Manufacturing Method of Semiconductor Device

Publications (1)

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KR970018542A true KR970018542A (en) 1997-04-30

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KR1019950032962A KR970018542A (en) 1995-09-29 1995-09-29 Capacitor Manufacturing Method of Semiconductor Device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100338848B1 (en) * 1998-02-03 2002-05-30 가네꼬 히사시 Fabrication method of semiconductor device with hsg configuration

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100338848B1 (en) * 1998-02-03 2002-05-30 가네꼬 히사시 Fabrication method of semiconductor device with hsg configuration

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