KR960036530A - PAL type burst synchronization control method and circuit - Google Patents

PAL type burst synchronization control method and circuit Download PDF

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Publication number
KR960036530A
KR960036530A KR1019950005614A KR19950005614A KR960036530A KR 960036530 A KR960036530 A KR 960036530A KR 1019950005614 A KR1019950005614 A KR 1019950005614A KR 19950005614 A KR19950005614 A KR 19950005614A KR 960036530 A KR960036530 A KR 960036530A
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KR
South Korea
Prior art keywords
signal
synchronization
burst
control circuit
synchronization control
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KR1019950005614A
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Korean (ko)
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KR100250126B1 (en
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이방진
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이대원
삼성항공산업 주식회사
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Priority to KR1019950005614A priority Critical patent/KR100250126B1/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/44—Colour synchronisation
    • H04N9/455—Generation of colour burst signals; Insertion of colour burst signals in colour picture signals or separation of colour burst signals from colour picture signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N11/00—Colour television systems
    • H04N11/06—Transmission systems characterised by the manner in which the individual colour picture signal components are combined
    • H04N11/12—Transmission systems characterised by the manner in which the individual colour picture signal components are combined using simultaneous signals only
    • H04N11/14—Transmission systems characterised by the manner in which the individual colour picture signal components are combined using simultaneous signals only in which one signal, modulated in phase and amplitude, conveys colour information and a second signal conveys brightness information, e.g. NTSC-system
    • H04N11/16—Transmission systems characterised by the manner in which the individual colour picture signal components are combined using simultaneous signals only in which one signal, modulated in phase and amplitude, conveys colour information and a second signal conveys brightness information, e.g. NTSC-system the chrominance signal alternating in phase, e.g. PAL-system
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/745—Circuitry for generating timing or clock signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H01L2924/1421—RF devices
    • H01L2924/14211—Voltage-controlled oscillator [VCO]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/234—Indexing scheme relating to amplifiers the input amplifying stage being one or more operational amplifiers

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

본 발명은 PAL 방식의 버스트 동기 제어방식 및 회로에 관한 것으로서 전압제어발진기로써 버스트신호를 발생시키는 단계; 상기 버스트신호와 주 클럭신호의 1/2 분주신호와의 위상비교신호를 출력하는 단계; 아날로그 스위치로써 동기모드를 구분하는 단계; 상기 동기모드가 내부동기모드인 경우, 상기 위상비교신호로써 상기 전압발진기를 동기 제어하는 단계; 그리고 상기 동기모드가 전원동기모드 또는 외부동기모드인 경우, 전원신호 또는 외부신호로써 상기 전압제어발진기를 동기 제어하는 단계;를 포함한 것을 특징으로 하여 외부동기 및 전원동기와 같은 추가적인 동기 구현이 가능해짐에 따라 다른 시스템과 결합시 동기모드에 따른 호환성 (compatibility)이 증진된다.The present invention relates to a burst synchronization control method and circuit of the PAL method comprising the steps of: generating a burst signal with a voltage controlled oscillator; Outputting a phase comparison signal between the burst signal and the 1/2 division signal of the main clock signal; Distinguishing a synchronous mode with an analog switch; If the synchronization mode is an internal synchronization mode, synchronously controlling the voltage oscillator with the phase comparison signal; When the synchronization mode is a power synchronization mode or an external synchronization mode, synchronously controlling the voltage controlled oscillator with a power signal or an external signal; further synchronization can be realized such as external synchronization and power synchronization. This improves compatibility with synchronization mode when combined with other systems.

Description

PAL 방식의 버스트 동기 제어방법 및 회로PAL type burst synchronization control method and circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 PAL 방식의 버스트 동기 제어방법을 나타낸 개념도이다.2 is a conceptual diagram illustrating a burst synchronization control method using a PAL method according to the present invention.

Claims (11)

전압제어발진기로써 버스트신호를 발생시키는 단계; 상기 버스트신호와 주 클럭신호의 1/2 분주신호화의 위상비교신호를 출력하는 단계; 아날로그 스위치로써 동기모드를 구분하는 단계; 상기 동기모드가 내부동기모드인 경우, 상기 위상비교신호로써 상기 전압발진기를 동기 제어하는 단계; 그리고 상기 동기모드가 전원동기모드 또는 외부동기모드인 경우 전원신호 또는 외부신호로써 상기 전압제어발진기를 동기 제어하는 단계;를 포함한 것을 특징으로 하는 PAL방식의 버스트 동기 제어방법.Generating a burst signal with a voltage controlled oscillator; Outputting a phase comparison signal of 1/2 divisional signalization of the burst signal and the main clock signal; Distinguishing a synchronous mode with an analog switch; If the synchronization mode is an internal synchronization mode, synchronously controlling the voltage oscillator with the phase comparison signal; And synchronously controlling the voltage controlled oscillator with a power signal or an external signal when the synchronous mode is a power synchronous mode or an external synchronous mode. 영상신호처리를 하기 위한 각종 클럭 및 CCD 구동클럭을 발생시키는 타이밍부; 상기 타이밍부에서 출력되는 주 클럭신호의 1/2 분주신호에 의거하여 각종 동기 펄서를 발생시키는 동기신호발생부; 그리고 상기 동기신호발생부에서 발생되는 위상비교신호에 의거하여 동기된 버스트신호를 발생시키는 버스트동기제어부;를 포함한 것을 특징으로 하는 PAL방식의 버스트 동기 제어회로.A timing unit for generating various clocks and CCD driving clocks for image signal processing; A synchronization signal generator for generating various synchronization pulses based on a 1/2 division signal of the main clock signal output from the timing unit; And a burst synchronization controller for generating a synchronized burst signal based on a phase comparison signal generated by the synchronization signal generator. 제2항에 있어서 상기 타이밍부가, 주 클럭신호의 1/2 분주클럭신호를 발생시키는 것을 그 특징으로 하는 PAL 방식의 버스트 동기 제어회로.3. The burst synchronization control circuit of claim 2, wherein the timing section generates one-half divided clock signal of the main clock signal. 제2항에 있어서 상기 동기신호발생부가, 동기신호발생기와 연산증폭기를 갖춘 것을 그 특징으로 하는 PAL 방식의 버스트 동기 제어회로.3. The burst synchronization control circuit of claim 2, wherein the synchronization signal generator includes a synchronization signal generator and an operational amplifier. 제4항에 있어서 상기 동기신호발생기가, 한 개의 집적회로인 것을 특징으로 하는 PAL 방식의 버스트 동기 제어회로.The burst synchronization control circuit of claim 4, wherein the synchronization signal generator is one integrated circuit. 제4항에 있어서 상기 연산증폭기가 상기 동기신호발생기에서 발생되는 위상비교신호를 증폭시키는 것을 그 특징으로 하는 PAL 방식의 버스트 동기 제어회로.5. The burst synchronization control circuit of claim 4, wherein the operational amplifier amplifies a phase comparison signal generated by the synchronization signal generator. 제4항에 있어서 상기 동기신호발생기가, 버스트신호와 주 클럭신호의 1/2 분주신호와의 위상비교신호를 출력하는 것을 그 특징으로 하는 PAL 방식의 버스트 동기 제어회로.5. The PAL burst synchronization control circuit according to claim 4, wherein the synchronization signal generator outputs a phase comparison signal between the burst signal and the 1/2 division signal of the main clock signal. 제2항에 있어서 상기 버스트동기제어부가, 아날로그 스위치, 전압제어발진기, 그리고 낸드게이트를 갖춘 것을 그 특징으로 하는 PAL 방식의 버스트 동기 제어회로.The burst synchronization control circuit of claim 2, wherein the burst synchronization control unit includes an analog switch, a voltage controlled oscillator, and a NAND gate. 제8항에 있어서 상기 전압제어발진기가 가변용량다이오드와 수정진동자를 갖춘 것을 그 특징으로 하는 PAL 방식의 버스트 동기 제어회로.9. The PAL burst synchronization control circuit according to claim 8, wherein the voltage controlled oscillator includes a variable capacitance diode and a crystal oscillator. 제9항에 있어서 상기 수정진동자가, PAL 방식에 맞는 17.73NHz의 버스트신호를 발진시키는 것을 그 특징으로 하는 PAL 방식의 버스트 동기 제어회로.10. The PAL system burst synchronization control circuit according to claim 9, wherein the crystal oscillator oscillates a burst signal of 17.73 NHz that conforms to the PAL system. 제8항에 있어서 상기 낸드게이트가, 상기 전압제어발지기의 출력 파형을 정형시키는 것을 그 특징으로 하는 PAL 방식의 버스트 동기 제어회로.The burst synchronization control circuit according to claim 8, wherein the NAND gate shapes an output waveform of the voltage controlled oscillator. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950005614A 1995-03-17 1995-03-17 Method and circuit for controlling burst synchronization of pal-type KR100250126B1 (en)

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KR1019950005614A KR100250126B1 (en) 1995-03-17 1995-03-17 Method and circuit for controlling burst synchronization of pal-type

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Application Number Priority Date Filing Date Title
KR1019950005614A KR100250126B1 (en) 1995-03-17 1995-03-17 Method and circuit for controlling burst synchronization of pal-type

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KR960036530A true KR960036530A (en) 1996-10-28
KR100250126B1 KR100250126B1 (en) 2000-03-15

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KR100713391B1 (en) * 2003-11-27 2007-05-04 엘지전자 주식회사 Apparatus for conversing sync signal in black and white camera line-lock

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