KR200212537Y1 - Apparatus for synchronization between frame pulse and clock signal - Google Patents

Abstract

The present invention is to provide a synchronization device of the frame pulse and the clock signal to enable the synchronization of the frame pulse and the clock signal to overcome the problems such as data loss or system malfunction caused by the signal phase difference. A main clock generation stage for generating a main clock using an external clock and a frame pulse; A reset signal is generated by an external clock and a frame pulse supplied to the main clock generator, and receives a main clock from the main clock generator to synchronize phases of the clock signals with the reset signals when generating a plurality of clock signals. It is composed of clock synchronous stages, so that even if it is not synchronized between the frame pulse and the main clock, the phase of each clock signal generated using the main clock can be synchronized with each other, which can be caused when the clock signals are not synchronized. It can prevent system malfunction or loss of transmission data.

Description

Apparatus for synchronization between frame pulse and clock signal}

The present invention relates to an apparatus for synchronizing frame pulses and clock signals to enable synchronization of frame pulses and clock signals to overcome problems such as data loss or system malfunction caused by signal phase differences.

In general, in a system having a plurality of functional units and each functional unit processing a plurality of signals in real time, phases between clock signals used in processing each signal are synchronized using frame pulses.

That is, in a system using a plurality of clock signals having different periods, the phases between clock signals are synchronized so that signals processed by each functional unit can be interpreted and used by other functional units.

The prior art for clock signal synchronization will now be described.

First, FIG. 1 is a block diagram of a conventional clock signal synchronizing apparatus. FIG. 2 is a timing diagram illustrating a case of synchronizing a 2M clock signal in the apparatus of FIG. 1, and FIG. 3 is an apparatus of FIG. Is a timing diagram illustrating a case where synchronization of a frame pulse and a clock signal does not match.

As shown in FIG. 1, the 4M clock is generated using the frame pulse FS and the 8M clock. Then, the generated main clock PCLK is generated using the generated 4M clock and 8M clock.

The plurality of clock generation units 12, 13, and 14 may generate various clock signals required in the system by using the main clock PCLK and the frame pulse FS. At this time, each clock generator 12, 13, 14 processes the signal input to each terminal to output a clock signal of various frequencies.

The frame pulse FS and the clock signal of 8M are supplied from a unit that controls each channel unit. Various clock signals are generated using the frame pulse FS and the clock signal of 8M, and each generated clock signal is synchronized with the frame pulse FS as shown in the timing diagram of FIG. 4A.

The clock signal generation operation will be described in more detail, and the frame pulse FS and the 8M clock are inverted and input to the JK flip-flop 11. The signal output from the JK flip-flop 11 is again inverted and output as a 4M clock signal. Then, the D flip-flop 15 receives the generated 4M clock signal and the 8M clock signal supplied from an external unit to generate the main clock PCLK.

The main clock PCLK and the frame pulse FS are inputted to the clock generators 12, 13, and 14, and each clock generator 12, 13, 14 when the frame pulse FS is high. The input of the LOAD terminal of is in the low state.

The input to the LOAD terminal of each clock generator 12, 13, 14 becomes a selection signal for the signal input to the clock generator. When the selection signal is in the low state, the input of the D terminal is selected, and in the high state, the input of the T terminal is selected.

Thus, when the signal input to the D terminal is low, when the frame pulse FS is high, the outputs of the clock generators 12, 13, and 14, QA, QB, QC, and QD, are all low.

In the second clock of PCLK, which is the main clock, the frame pulse FS goes low. Therefore, the input to the LOAD terminal of each clock generator 12, 13, and 14 becomes high and the signal input to the T terminal is received. Will be chosen. Then, only the QA terminals of the clock generators 12, 13, and 14 output a high state signal.

Through the above operation, the output of QA, QB, QC, and QD is synchronized to the frame pulse FS.

However, the above-described prior art causes a problem when the frame pulse and the PCLK clock are not synchronized. That is, as shown in FIG. 4B, when the PCLK clock rises slightly ahead of the frame pulse, there is a problem in that the frame pulse FS cannot synchronize the phase of each clock signal generated from the PCLK. In particular, using a clock signal that is not synchronized may cause malfunction of the system and loss of transmission data.

Therefore, the present invention is proposed to solve the conventional problems as described above, an object of the present invention is to enable the synchronization of the frame pulse and the clock signal to overcome the problems such as data loss or system malfunction caused by the signal phase difference The present invention provides a device for synchronizing one frame pulse and a clock signal.

In order to achieve the above object, the apparatus for synchronizing a frame pulse and a clock signal according to the present invention includes a main clock generating stage for generating a main clock using an external clock and a frame pulse; A reset signal is generated by an external clock and a frame pulse supplied to the main clock generator, and receives a main clock from the main clock generator to synchronize phases of the clock signals with the reset signals when generating a plurality of clock signals. It is characterized by the technical configuration of the clock synchronization stage.

1 is a block diagram of a clock signal synchronization device according to the prior art,

FIG. 2 is a timing diagram illustrating a case of synchronizing a 2M clock signal in the apparatus according to FIG. 1;

3 is a timing diagram illustrating a case where frame pulses and clock signals are not synchronized in the apparatus of FIG. 1;

4 is a block diagram of an apparatus for synchronizing a frame pulse and a clock signal according to an embodiment of the present invention;

5 is an exemplary configuration diagram of a block for generating a clock signal before synchronization in FIG. 4;

6A is a signal timing diagram of the apparatus according to FIG. 5,

6b is a signal timing diagram of the apparatus according to FIG.

FIG. 7A is a signal timing diagram when the phase of the frame pulse and the main clock do not match in the apparatus of FIG. 5;

FIG. 7B is a signal timing diagram between clocks when the phase of the frame pulse and the main clock do not match in the apparatus of FIG.

Explanation of symbols on the main parts of the drawings

50: main clock generator 60A, 60B: clock generator

61A, 61B: Clock Generation Stage

Hereinafter, the configuration and operation of the present invention will be described based on the embodiment of the technical idea of the apparatus for synchronizing the frame pulse and the clock signal according to the present invention.

First, FIG. 4 is a block diagram of a device for synchronizing a frame pulse and a clock signal according to an embodiment of the present invention, and FIG. 5 is a block diagram of a block generating each clock signal before synchronization in FIG. 4. Fig. 6A is a signal timing diagram of the apparatus according to Fig. 5, Fig. 6B is a signal timing diagram of the apparatus according to Fig. 4, and Fig. 7A is a signal when the phase of the frame pulse and the main clock do not match in the apparatus according to Fig. 5. Fig. 7B is a timing diagram of signals between clocks when the phases of the frame pulse and the main clock do not match in the apparatus of Fig. 4.

As shown in FIG. 4, a suitable embodiment of the present invention includes: a main clock generation stage 50 for generating a main clock using an external clock and a frame pulse; A reset signal is generated by an external clock and a frame pulse supplied to the main clock generator 50, and receives the main clock from the main clock generator 50, and generates each clock signal as the reset signal when generating a plurality of clock signals. It consists of clock synchronization stages 60A and 60B for synchronizing phases between signals.

The operation of the device configured as described above is as follows.

The generating block of each signal processed in the apparatus according to the present invention is shown in FIG. That is, the generation block generates a clock signal before the phases are synchronized with each other, and the phase synchronization of the generated clock signal is performed in the apparatus of FIG. 4.

In detail, the frame pulse FS and the clock of 8M which are supplied from an external SCU (unit for controlling channel units) in FIG. 5 are respectively supplied to the main clock generating stage 50 and the clock generating units 61A and 61B. Is entered.

The main clock generator 50 generates the PCLK as the main clock using the frame pulse FS and the clock of 8M, and outputs the generated PCLK to the clock generators 61A and 61B. The clock generators 61A and 61B generate an RM signal by performing an OR operation on the frame pulse FS and an 8M clock, and use the generated RM signal as a reset signal for a plurality of D flip-flops.

The main clock generated by the main clock generator 50 is input to a plurality of D flip-flops provided in the clock generators 61A and 61B. In the plurality of D flip-flops provided in the clock generators 61A and 61B, the output of each clock signal is controlled according to the main clock, thereby allowing clocks such as 2M, 1M, 512K, 256K, 128K, 64K, 32K, 16K, and 8K. Will output a signal.

The timing of the clock signal generated as described above is illustrated in Fig. 6A, but the synchronization between the generated clock signals is not synchronized. On the other hand, the RM signal has a period different from that of the frame pulse FS, but is synchronized at the rising edge.

Each generated clock signal is synchronized with the frame pulse FS. The clock synchronization stages 60A and 60B shown in FIG. 4 include clock generators 61A and 61B, and each clock signal outputted from the clock generators 61A and 61B uses a plurality of D flip-flops. This shifts the phase by half the period of 2M clock.

The timing of each signal being phase shifted at the clock synchronization stages 60A and 60B is illustrated in FIG. 6B. That is, in FIG. 6B, the 1M clock and the 512K clock are synchronized with the rising edge of the frame pulse FS by phase transition, so that the phases of the 2M clock, the 1M clock, and the 512K clock are synchronized with each other.

The device operating as described above may overcome the problem caused when the synchronization between the frame pulse FS and the main clock PCLK is not correct.

First, in the case where the device according to the present invention is mounted in the system to generate each clock signal, the clock generated in the first frame pulse FS is not used, so the first part of each clock is ignored.

Therefore, timing between each signal is made from the second frame pulse FS as shown in FIG. 7A.

At this time, if the phase between the frame pulse FS and the main clock PCLK is not synchronized, the signal having the timing shown in Fig. 6B by phase shifting each clock signal having the timing as shown in Fig. 6A using the apparatus according to the present invention. To be

With this operation, the inter-myth timing shown in Fig. 7A can be switched to the inter-signal timing shown in Fig. 8B. Therefore, in FIG. 8B, even when the frame pulse FS and the main clock PCLK are not synchronized, the phases of the 2M clock, the 1M clock, and the 512K clock are synchronized.

This operation is not limited to the clock of the specific period illustrated above, but is applied to the clock signal of all periods generated in the unit, and the main clock is used even when it is not synchronized between the frame pulse FS and the main clock PCLK. The phases of the generated clock signals can be synchronized with each other.

While the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Therefore, the above description does not limit the scope of the present invention defined by the limits of the following utility model registration claims.

As described above, the apparatus for synchronizing the frame pulse and the clock signal according to the present invention can synchronize the phase of each clock signal generated by using the main clock even when not synchronized between the frame pulse and the main clock. There is an effect to prevent system malfunction or transmission data loss, which may be caused when the clock signal is not synchronized.

Claims (4)

A main clock generation stage for generating a main clock using an external clock and a frame pulse; A clock for generating a reset signal using an external clock and a frame pulse supplied to the main clock generating stage, and receiving a main clock from the main clock generating stage and synchronizing a phase between the clock signals as the reset signal when generating a plurality of clock signals. A device for synchronizing a frame pulse with a clock signal, characterized in that the synchronization stage. The method of claim 1, And the clock synchronizing stage performs an AND operation on the external clock and the frame pulse so that a reset signal of the same period as the external clock is generated while the frame pulse is generated. The method of claim 1, The clock synchronizing stage includes a plurality of D flip-flops at the output terminal of the clock signal. When each D flip-flop receives a reset signal, the clock signal generated from the first frame pulse is not used and the clock is generated from the second frame pulse. Even if a signal is used And controlling the phase of each clock signal, thereby synchronizing the phase between each clock signal irrespective of whether the frame pulse and the main clock are synchronized. The method of claim 3, wherein Each D flip-flop resets the phase of the clock signal output to the Q terminal according to the reset signal while the frame pulse and the main clock are high, and the reset signal is set to each D flip-flop without a phase difference. And a plurality of D flip-flops to reset the phase of the clock signal at the same time.