KR870010734A - Synchronous signal generator - Google Patents

Synchronous signal generator Download PDF

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Publication number
KR870010734A
KR870010734A KR870003693A KR870003693A KR870010734A KR 870010734 A KR870010734 A KR 870010734A KR 870003693 A KR870003693 A KR 870003693A KR 870003693 A KR870003693 A KR 870003693A KR 870010734 A KR870010734 A KR 870010734A
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KR
South Korea
Prior art keywords
signal
circuit
output
bias
output transistor
Prior art date
Application number
KR870003693A
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Korean (ko)
Other versions
KR930003564B1 (en
Inventor
히로야쓰 기시
히로미 아라이
Original Assignee
이우에 사또시
상요덴기 가부시기 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 이우에 사또시, 상요덴기 가부시기 가이샤 filed Critical 이우에 사또시
Publication of KR870010734A publication Critical patent/KR870010734A/en
Application granted granted Critical
Publication of KR930003564B1 publication Critical patent/KR930003564B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising

Abstract

내용 없음No content

Description

동기신호 발생장치Synchronous signal generator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 본 발명의 한 실시예를 도시한 회로도.1 is a circuit diagram showing one embodiment of the present invention.

제 3 도는 복합 동기신호가 리셋트 신호로 변환되는 모양을 나타내는 파형도.3 is a waveform diagram showing how a composite synchronization signal is converted into a reset signal.

제 4 도는 출력핀(11)에서 발생하는 출력 파형을 나타내는 파형도.4 is a waveform diagram showing an output waveform generated at the output pin 11;

Claims (1)

영상신호 중의 수직 동기신호에 따른 신호가 리셋트신호로서 인가되고, 상기 영상신호 중의 수평 동기 신호에 따른 신호가 클럭신호로서 인가되는 분주회로를 사용해서 수직 구동 펄스를 발생시키는 카운트다운 방식의 동기신호 발생장치에 있어서, 상기 분주회로의 출력신호가 인가되며, 출력단에 수직 구동 펄스를 발생하는 출력트랜지스터와, 이 출력트랜지스터의 베이스에 바이어스전압을 인가하는 바이어스회로와, 상기 분주회로가 소정의 카운트를 행한 때, 상기 바이어스회로를 제어하고, 이 바이어스회로의 출력 바이어스 전압을 변화시키는 수단으로 이루어지며, 상기 출력 트랜지스터의 출력단에 있어서의 전압을 상기분주 회로의 카운트 수에 따라서 절환하도록 한 것을 특징으로 하는 동기신호 발생장치.A countdown type synchronization signal that generates a vertical drive pulse by using a division circuit in which a signal corresponding to the vertical synchronization signal in the video signal is applied as a reset signal and a signal according to the horizontal synchronization signal in the video signal is applied as a clock signal. In the generator, an output signal of the division circuit is applied, an output transistor for generating a vertical driving pulse at an output terminal, a bias circuit for applying a bias voltage to the base of the output transistor, and the division circuit generates a predetermined count. And a means for controlling the bias circuit and changing the output bias voltage of the bias circuit, wherein the voltage at the output terminal of the output transistor is switched in accordance with the count number of the frequency divider circuit. Synchronous signal generator. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870003693A 1986-04-18 1987-04-17 Synchronizing pulse generating circuit KR930003564B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP90584 1986-04-18
JP?61-90584 1986-04-18
JP61090584A JPS62247679A (en) 1986-04-18 1986-04-18 Synchronizing signal generator

Publications (2)

Publication Number Publication Date
KR870010734A true KR870010734A (en) 1987-11-30
KR930003564B1 KR930003564B1 (en) 1993-05-06

Family

ID=14002493

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870003693A KR930003564B1 (en) 1986-04-18 1987-04-17 Synchronizing pulse generating circuit

Country Status (2)

Country Link
JP (1) JPS62247679A (en)
KR (1) KR930003564B1 (en)

Also Published As

Publication number Publication date
KR930003564B1 (en) 1993-05-06
JPH0553353B2 (en) 1993-08-09
JPS62247679A (en) 1987-10-28

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