KR930003564B1 - Synchronizing pulse generating circuit - Google Patents

Abstract

No content.

Description

Synchronous Signal Generator

1 is a circuit diagram showing one embodiment of the present invention.

2 is a circuit diagram showing a conventional synchronization signal generator.

3 is a waveform diagram showing how a composite synchronization signal is converted into a reset signal.

4 is a waveform diagram showing an output waveform generated at the output pin 11. FIG.

5 is a circuit diagram showing the configuration of the frequency divider circuit of FIG.

6 is an output waveform diagram of each flip-flop constituting the frequency divider circuit of FIG.

7 is an output waveform diagram of an output terminal C of FIG.

8 is an output waveform diagram of the AND gate 53 of FIG.

* Explanation of symbols for main parts of the drawings

8: dividing circuit 24: second transistor

25 fourth transistor 26 bias circuit

33: output transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a countdown type synchronization signal generator in a TV receiver, and more particularly, to a synchronization signal device suitable for ICization.

In the TV receiver, a signal of frequency nfH of an integer multiple of the horizontal frequency fH is generated in synchronization with the horizontal synchronizing signal, and the signal is divided according to the vertical synchronizing signal to generate a signal of the vertical frequency fv. Vertical deflection circuits are known which perform vertical deflection using a. An example of such a circuit IC is the IC LA 7620 for image, color, and deflection circuit described in page 1000 of the 85th Semiconductor Handbook, Monolithic Bipolar Integrated Circuit, issued March 20, 60. . 2 shows a circuit in which the synchronization signal generator is extracted from the IC. In Fig. 2, reference numeral 1 denotes an IC, and an image signal from an image detection circuit (not shown) is applied to the composite synchronous separation circuit 3 through the input pin 2, and the horizontal and vertical synchronization signals and the like. The composite synchronization signal of is separated. Since this composite synchronizing signal is applied to the vertical synchronizing separation circuit 7 composed of the integrating circuit 4, the clamp circuit 5, and the transistor 6, the pulse signal synchronized with the vertical synchronizing signal of the collector of the transistor 6. The pulse signal is applied to the frequency divider circuit 8 as a reset signal.

On the other hand, the signal issuing circuit 9 to which the composite synchronizing signal obtained from the composite synchronizing separation circuit 3 is applied generates a frequency 2fH signal twice the horizontal frequency fH synchronized with the horizontal synchronizing signal. The signal is applied to the division circuit 8 as a clock signal. For this reason, the dividing circuit 8 divides the signal of 2fH by 1/525 in accordance with the pulse of the vertical synchronizing separation circuit 7. As a result, an output signal of vertical frequency fv is applied to the base of the output transistor 10 in the division circuit 8, and a driving pulse for driving the vertical deflection circuit 12 is obtained at the output pin 11. Can be.

Therefore, according to the circuit of FIG. 2, a driving pulse for vertical deflection of an image signal can be obtained.

In the circuit of FIG. 2, the waveform of the vertical drive pulse generated at the output pin 11 may be observed when checking the division operation of the IC 1, for example, the division circuit 8. However, in order to know whether or not the vertical drive pulse is generated by an accurate counting operation, it is necessary to check the interval of the vertical drive pulse, so there is a problem that takes time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and includes: an output transistor to which an output signal of a frequency divider circuit is applied and which generates a vertical driving pulse at an output terminal; A bias circuit which applies a bias voltage to the base of this output transistor; And means for controlling the bias circuit when the frequency divider circuit performs a predetermined count, and for changing the output bias voltage of the bias circuit.

According to the present invention, since the frequency division circuit operates to change the voltage obtained at the output terminal of the output transistor in the opposite direction to the vertical driving pulse when the predetermined count is performed, the frequency division circuit is observed by observing the waveform of the signal generated at the output terminal. You can easily check whether or not is operating normally.

(단, m≥1)의 커런트 미러(current mirror) 관계로 접속되어 있다. 또한, 제 1 도에 있어서 제 2 도와 동일한 회로 소자에 관해서는 동일한 부호를 붙이고, 그 설명을 생략한다.1 is a circuit diagram showing an embodiment of the present invention, where (13) is a first transistor to which a composite synchronization signal from the composite synchronization separation circuit 3 is applied to a base and performs a switching operation; (14) to (16) are first to third constant current transistors whose emitters are connected to a power supply (+ Vcc) through resistors 17 to 19, respectively; 20 is a transistor which performs a diode function to which a constant current is supplied from the first and second constant current transistors 14 and 15; (21) is a second transistor whose constant current is supplied to the collector from the third constant current transistor 16 and whose base is connected to the collector of the first transistor 13; (22) is a charge / discharge capacitor which charges and discharges by turning on / off this second transistor 21; (23) is a comparison circuit in which one end of the charge / discharge capacitor 22 is connected to a positive (+) input terminal and a reference power source is connected to a negative (-) input terminal; 24 is a third transistor to which the first divided output of the divider circuit 8 is applied to the base and whose emitter is grounded; (25) is a fourth transistor to which the second divided output of divider circuit 8 is applied to the base, and the emitter is grounded; (26) is a bias circuit for temperature compensation consisting of resistors 27, 28 and 29 and diodes 30, 31 and 32; 33, the base is connected to the bias circuit 26, the collector is connected to the power supply through the transistor 34 and the resistor 35 to perform the diode function, the emitter to the load through the output pin 11 Is an output transistor connected to a variable resistor 36 attached to the outside. In addition, the transistor 34 performing the diode function may be connected to the first to third constant current transistors 14 to 16.

However, they are connected in a current mirror relationship of m≥1. In addition, in FIG. 1, the same code | symbol is attached | subjected about the circuit element same as 2nd degree, and the description is abbreviate | omitted.

In FIG. 1, a composite synchronization signal such as the third (a) diagram is extracted from the video signal applied to the composite synchronization separation circuit 3 via the input pin 2. As shown in FIG. This composite synchronization signal is applied to the signal generating circuit 9 and to the base of the first transistor 13 at the same time. When a rectangular pulse corresponding to the vertical driving pulse is applied to the base of the first transistor 13, the first transistor 13 is turned on and the second transistor 21 is turned off, so that the charge / discharge capacitor 22 has a third A constant current is charged by the constant current transistor 16 with the current Io, and the terminal voltage thereof is applied to the positive input terminal of the comparison circuit 23. If no rectangular pulse is applied to the base of the first transistor 13, the first transistor 13 is turned off and the second transistor 21 is turned on. Since the transistor 20 and the second transistor 1 which perform the diode function have a configuration of a current mirror circuit, the currents of the first and second constant current transistors 14 and 15 are applied to the transistor 20 that performs the diode function. When the current 2Io added with Io flows, the current Io of the third constant current transistor 16 and the discharge current Io of the charge / discharge capacitor 22 are added to the second transistor 21. 2Io) flows. Therefore, when the composite synchronization signal such as the third (a) diagram is applied to the base of the first transistor 13, the positive / positive capacitor of the third (b) diagram to the positive input terminal of the comparison circuit 23 ( The output signal of 22) is applied. Here, when the voltage of the reference power supply of the comparison circuit 23 is set as the dashed-dotted line of FIG. 3 (b), the rectangular pulse like FIG. 3 (c) is reset from the comparison circuit 23 to the division circuit 8. It is applied as a signal.

By the way, the frequency divider 8 is comprised by the same circuit as 5th degree | time. The pulses of the frequency 2fH supplied to the clock terminal X are divided in a frequency divider consisting of first to 10 T-FFs (FF: flip-flop circuits 37 to 46) that are cascaded. When the 256H-th (512) input pulses are counted after the frequency divider is reset, the Q output of the tenth T-FF 46 is at the "H" level. The signal of this "H" level is applied to one input of the NAND gate 47. As a result, while the output of the tenth T-FF 46 is in the "H" period, the inverted signal of the Q output of the fourth T-FF 40 is generated at the output terminal C as the second divided output. Therefore, the signal generated at the output terminal C becomes a period 8H (where H represents one period of the horizontal synchronization signal).

Further, when a reset pulse is applied to the reset terminal A, the first SR-FF 48 is set, and its Q output is applied to the D-FF 50 through the NOR gate 49. On the other hand, since the output terminal C of the D-FF 50 is connected to the clock terminal X, after the output of the NOR gate 49 is applied, the Q output occurs at the next clock pulse, and 0.5H The delayed Q output is applied to the divider as a reset signal. Further, since the Q output is applied to the set input of the second SR-FF 52 through the inverter 51, an output pulse which is the first divided output is generated at the output terminal B. In addition, since the second SR-FF 52 is reset when the frequency divider is releted and counted after 8H, the Q output returns to the "L" level. Therefore, an output pulse of 8.5H is generated at the output terminal B. FIG.

When the reset signal is not applied to the reset terminal which is the input terminal A, when the frequency divider counts 296H, all of the inputs of the AND gate 53 are at the "H" level, and the output is "H". Level to trigger the D-FF 50. As a result, the divider is reset and the second SR-FF 52 is set to generate an output pulse at the output terminal B. FIG. Therefore, the second SR-FF 52 is set by the reset signal applied to the input terminal A or the output signal of the AND gate 53.

6 shows output signal waveforms of the first to tenth T-FFs 37 to 46 in FIG. The clock signal of the frequency 2fH shown in FIG. 6 (a) is sequentially divided by the first through tenth T-FFs 37 through 46 to form a waveform as shown in FIGS. 6 (b) through (k). On the other hand, the output signal of the T-FF 40 and the output signal of the T-FF 46 shown in FIG. 7 (a) are applied to the NAND gate 47 of FIG. The waveform is generated. The signal corresponds to a signal as shown in FIG. 4 (b). The generation of the signal inverting every 4H ends at 296H. That is, as shown in FIG. 8, the signals of (a), (b), and (c) of FIG. 5 are applied to the AND gate 53 of FIG. . When the signal of FIG. 8 (d) becomes 296H, this signal is applied to the D-FF 50 through the NOR gate 49, and then the clock signal whose frequency is 2fH (0.5H) at 0.5H is D-FF. It is applied to the output terminal C of 50, and 2Q output becomes a "L" level. In addition, all of the first to tenth T-FFs 37 to 46 are reset. When the Q output of the D-FF 50 is at the "L" level, the SR-FF 52 is set, and the output of the output terminal B is at the "L" level {the output terminal D of FIG. H "level}.

As described above, when all of the first to tenth T-FFs 37 to 46 are reset, the output of the AND gate 53 is at the "L" level, and the D-FF ( 50). Therefore, the output of the D-FF 50 becomes the "H" level immediately after the clock signal 2fH immediately after that, and the reset of the first to tenth T-FFs 37 to 46 is released. As a result, referring to the waveform in FIG. 4 (b), when the count is completed up to 296H, the whole division circuit 8 starts to reset at a clock of 296.5H, and continues to reset between 296.5H and 297H. . This reset period of 0.5H corresponds to the 0.5H signal among the 8.5H signals in FIG. 4 (b). The Q output terminal B of the SR-FF 52 is at the "H" level at the timing of 296.5H, and maintains this state even after the reset is completed. On the other hand, the first to tenth T-FFs 37 to 46 start counting from 297H (= OH), and again generate a plurality of divided outputs as in the sixth degree. Then, when the signal of FIG. 6 (f) is applied to the reset terminal R of the SR-FF 52, the output terminal B of FIG. 5 is original after 8.5H period as the signal of FIG. 4 (b). Return to the position of.

Referring back to FIG. 1, in the case of NTSC, a vertical synchronization signal is generated at a period of 262.5H. Since the dividing circuit 8 performs the configuration and operation as described above, the second dividing output generated at the output terminal C of the dividing circuit 8 is at the "H" level up to 260H, and then "L" at every 4H, Repeat the "H" level. Therefore, the fourth transistor 25 turns on when the second divided output is at the "H" level, and shorts the resistor 29 and the diode 32 of the bias circuit 26. As a result, when the voltage of the output terminal D becomes the first predetermined value and the values of the resistors 27, 28, and 29 are all the same, the emitter voltage of the output transistor 33 becomes 1/2 Vcc. . When the divider circuit 8 counts up to 260H, the second divided output of the divider circuit 8 is at the "L" level, and the fourth transistor 25 is turned off. As a result, the voltage at the output terminal D becomes the second predetermined value, and the emitter voltage of the output transistor 33 is 2/3 Vcc. Next, when a vertical synchronizing signal equal to the third (c) degree at 261.5H is applied to the frequency divider circuit 8 at the input terminal A, it is reset to 262H, by the first frequency output at the output terminal B. The third transistor 24 is turned on, and the emitter voltage of the output transistor 33 becomes an earth potential. In addition, since the first divided output at the output terminal B turns off the third transistor 24 after 8.5H, the emitter voltage of the output transistor 33 becomes 1/2 Vcc again. As a result, the output voltage waveform of the emitter of the output transistor 33 is equal to the fourth (a) degree.

When the vertical synchronizing signal is not applied to the input terminal A, the second divided output at the output terminal C of the auxiliary circuit 8 after 260H is inverted at 4H cycles. The terminal voltage is reset to 296H by repeating 1/2 Vcc and 2/3 Vcc in 4H cycles, and at 296.5H, the third transistor 24 is turned on by the first divided output at the output terminal B. The emitter voltage of the transistor 33 becomes an earth potential. As a result, the output voltage waveform of the emitter of the output transistor 33 is the same as that of the fourth (b) diagram.

In this way, if the frequency divider circuit 8 is operating normally, when the normal video signal is applied to the input pin 2, the output voltage waveform of FIG. 4 (a) is generated at the output pin 11, and the video signal is generated. When not applied to the input pin 2, since the output voltage waveform of FIG. 4 (b) is generated at the output pin 11 by the self reset function of the frequency divider circuit 8, the frequency divider circuit inside the IC 1 is generated. The operation of (8) can be easily checked.

로 되고, 수직 동기 신호의 발생이 예상되는 기간에는

로 된다. 출력 트랜지스터(33)의 에미터와 콜렉터에 흐르는 전류가 동일하다고 생각해도 좋으므로, 다이오드 기능을 수행하는 트랜지스터(34)의 커런트 미러 관계로 있는 제1 내지 제3 정전류 트랜지스터(14 내지 16)에는

의 전류가 흐른다. 그 때문에, 전류

인 때에는 충·방전 콘덴서(22)의 충전 전류가 전류

인 때 보다 크게 되고, 수직 동기 신호의 검출 감도를 필요시에 올리 수 있으며, 약전계시에도 정밀도가 양호한 검출을 수행할 수 있다.On the other hand, as can be seen in FIGS. 4A and 4B, the emitter voltage of the output transistor 33 becomes high in the period in which the generation of the vertical synchronization signal is expected, and the value of the variable resistor 36 is set to Ro. In this case, the current flowing through the output transistor 33 is normally

In the period in which the generation of the vertical synchronization signal is expected,

It becomes Since the current flowing through the emitter and the collector of the output transistor 33 may be the same, the first to third constant current transistors 14 to 16 in a current mirror relationship of the transistor 34 performing the diode function may be considered.

Current flows. Therefore, the current

Is the charge current of the charge / discharge capacitor 22

It becomes larger than when, and it can raise the detection sensitivity of a vertical synchronizing signal as needed, and can perform the detection with high precision also in a weak electric field.

According to the present invention described above, since the waveform representing the operating state of the vertical driving pulse and the frequency divider is obtained at the output terminal of the output transistor, the function of the frequency divider circuit in the IC can be easily inspected, and at the same time, a specific test pin is used for the inspection. Since it is not necessary, a synchronization signal generator suitable for IC can be provided. Further, as in the embodiment, when the detection sensitivity is switched in accordance with the output signal generated by the emitter of the output transistor to detect the vertical synchronization signal, even if the level of the vertical synchronization signal in the weak field or the like decreases, the detection is sufficiently performed. can do.

Claims (1)

A countdown method in which a vertical drive pulse is generated by using a division circuit 8 in which a signal corresponding to a vertical synchronizing signal in a video signal is applied as a reset signal, and a signal according to a horizontal synchronizing signal in the video signal is applied as a clock signal. In the synchronizing signal generating apparatus of the present invention, an output signal of the frequency dividing circuit 8 is applied, and a bias voltage is applied to the base of the output transistor 33 and the output transistor 33 which generate a vertical driving pulse at the output terminal 11. Means 25 for controlling the bias circuit 26 and changing the output bias voltage of the bias circuit 26 when the bias circuit 26 and the frequency divider circuit 8 perform a predetermined count. And the voltage at the output terminal 11 of the output transistor 33 is switched in accordance with the count number of the frequency divider circuit 8. Value.

Images