SU409230A1 - DEVICE FOR CONTROLLING DIGITAL DEVICES OF POSITIVE EQUALIZATION - Google Patents

Description

I

The invention relates to the field of digital electrical measurement technology and can be used in digital measuring instruments and systems having high speed, a large number of bits and small dimensions, especially in micro or integral.

Devices for controlling digital Iribors of a digital equilibration are known, comprising a source of clock pulses, a balance indicator, potential memory triggers, coincidence circuits, and separation elements in the memory trigger control circuits.

The purpose of the invention is to simplify the circuit and increase the speed of the device without increasing or increasing the cost of equipment.

This is achieved by the fact that the output of each trigger is connected to the first input of the coincident circuit, the second input of the coincidence circuit is connected to the bus of the clock emulsions, the output through successively connected rectifier and the separator element to the input of the subsequent trntger, and two connected connected the diode is connected to the sync pulse bus.

FIG. Figure 1 shows a simplified diagram of the proposed device for four bits with the image of the switching circuits of memory triggers when the device is equipped with direct transistors (pnp); in fig. 2 — temporal voltage diagrams, but removing the operation of the device. The device contains a source / sync pulses with 2 (even) and 3 (odd) ta. Pulses and 4 reset buses, 5 balance indicator with output bus 6, potential triggers 7 for us, 8 coincidence circuit and separation elements - capacitors 9 Chains Included memory triggers.

Circuit 8 matches have two inputs, one of which, for example a diode one, is connected to the trigger outputs us, and the other input, for example, a resistor, to one of the clock

Shnn 2 nli about. The outputs of soviadeni circuits through an internally connected diode 10 and a capacitor 9 are connected to the trigger inputs of triggers 7 and they. The points of connection of the rectifying elements — the JO diodes and the capacitors 9 — through the electrolyte junction} 1e elements — the diodes // are connected to the bus 4 discharge.

The proposed construction of the switching circuits of memory triggers in the device simplifies the circuit and improves the speed

devices when testing the code without increasing and increasing the cost of equipment.

FIG. Figure 1 shows one of the possible options: iaHTOiB of constructing prices for turning off the triggers of these types on the coincidence circuits 12. One and,-:

The input of the co-operation (pulse) circuits is connected to the outputs of the memory trigger 7, the other input (output) is connected to the output bus 6 of the balance indicator, and the outputs of the current circuitry to the power off inputs of the previous memory triggers.

The device operates as follows.

In the initial position, the tritggers 7 are in the state of "O - on the single outputs of the flip-flops (shaded half) the voltage has a zero level (close to the O in). Capacitors 9 are discharged, tire 4 is shorted to ground with a key in the synchronous pulses source, on the bus 3 odd clock pulses — a voltage level of zero, on the bus 2 even clock pulses — a unit voltage level.

The operation of the circuit is permitted when the bus 4 is disconnected from the ground and when a unit voltage level Wabr is applied to it. The first odd clock pulse voltage across bus 3 passes through diode 10 and capacitor 9 to turn on the input of the first memory trigger, forming a turn-on voltage, under the influence of which the first trigger is set to position 1 - unit voltage level f / i at a single output this trigger. The capacitor 9 in the turn-on circuit of the first trigger is charged (t / ic diagram), as a result of which the turn-on voltage t / iBi.-. It has the form of a differentiated pulse, the duration of which is shorter than the duration of the voltage pulse. At the inputs of the inclusion of other odd memory triggers, the first pulse And does not pass, since the corresponding circuits 8 are not prepared to match (zero voltage level at the single outputs of the even triggers are us).

At the end of the first imulse U on bus 3, bus 2 receives the first even clock pulse voltage LI. At this moment, only the combination of the second trigger circuit is prepared for operation, so the first pulse U passes through the coincidence circuit 8, the diode 10 and the capacitor 9 to the trigger input of the second trigger, which triggers the second trigger to the position " 1 - The U Uash on its single output has a single level. The capacitor 9 in the turn-on circuit of the second trigger is charged (f / 2c diagram), as a result of which the duration of the C / 2E imuluise is less than the duration of the clock pulse U. The first pulse U does not arrive at the inputs of the other even triggers, since the corresponding schemes 8 are not prepared . The voltage drop Vz from the output of the second flip-flop is fed to the coincidence circuit 12 in the tripping circuit of the first tripper. If bus 6 comes from a rebalance sipnal balance indicator (single voltage level t / e), then the first trigger is reset to "O. When the voltage bb is zero (underbalance), the first trigger remains unsettled due to the fact that the off pulse does not pass to its zero input (coincidence circuit 12 is closed).

The f / z voltage from the output of the second flip-flop: Gera prepares for operation a circuit 8 of coincidence in the switch-on circuit of the third flip-flop. When the second odd pulse U arrives via bus 3 (at the end of the first even pulse U), the voltage drop U passes through coincidence circuit 8, diode 10, capacitor 9 to the input of the third trigger, producing a voltage bzok - under the influence of which the third trigger set to position "1. The voltage drop t / s from the output: yes, this trigger enters the circuit 12 of the coincidence in the off circuit of the second trigger and, in the case of rebalance, resets it to "O. Similarly, P | roisOdIt includes the inclusion of subsequent memory triggers and the formation of off-pulse in the case of rebalance.

In this case, the capacitor 9 in the switching circuit of each successive trigger is charged.

fully during one clock cycle, if the previous trigger is not reset to "O, or is not fully charged, if the previous trigger is reset to" O. And in either case, the next clock pulses And and U

cannot pass to the trigger input, which has already been turned on, since in the first case the charge current of capacitor 9 is zero (the charge on the capacitor remains almost unchanged during the equilibration time), and

in the second case, a scheme 8 was not prepared for the previous trigger.

To maintain the charge of capacitors during equilibration, the inverse resistances of diodes 10 and 11 should be sufficient

large, at the same time, the direct resistances of the diodes 10 and the resistances of the capacitor charge circuits must provide a charge during a single clock pulse, I or b. These requirements are easily performed by flint diodes with the number of bits up to 20.

Thus, it is achieved alternately and one-time activation of each memory trigger during one time, balance and independently of the code generated in the triggers,

which is necessary when the bottom is balanced.

The code formed in the process of balancing can be removed in a sequential form, for example, from the balance indicator bus 6 (reverse code), as well as in parallel from memory triggers. In the first case, the last memory trigger is not necessary to reset at rebalance; in the second case

for reset, you can use the pulse of the end of the measurement from the source of clock pulses and put the coincidence circuit 12 on the switch off circuit of the last trigger. At the end of the measurement, the memory triggers

set to the initial position "O.

The flip-flops can be reset by closing the tire 4 to the ground (signal - resetting the source 1 clock pulses), if the capacitor 9 has enough time to charge up to a sufficient amount to turn off the previous bit (when rebalance). In this case, the capacitors are discharged to the enable inputs of the memory trigger and set them to the "O (positive impulses {Url, t / 2ui -i, etc.") position.

If the circuit is designed in such a way that the charge of capacitors is insufficient for resetting the flip-flops, then it is necessary to install a special waste circuit.

At the end of the reset, the circuit is ready for the next balancing cycle.

Thus, in the switch-on circuit of each memory trigger of a matching circuit with two inputs, two diodes and a capacitor connected in the described manner, the device operates at one bit equilibrium, and the operating modes of all elements do not depend on the number of memory trigger, and the amplitude of the pulses for switching on the memory triggers depends on the number of triggers (bits). This simplifies the scheme, its calculation and configuration. The number of elements used is even smaller than in known schemes with series-connected chains of coincidence circuits.

At the same time, the speed of the device significantly improves when the code is processed, so

Like all capacitors in the memory trigger circuit, they are prepared before the start of the measurement with a waste pulse. In the known devices, each capacitor G, the start circuit of each trigger is prepared. 1 is transmitted to pass the turn-on impulse during the measurement immediately before switching on the corresponding discharge (trigger), and since the discharge is switched on in turn, the speed is limited by the total recharge time of all capacitors. In the proposed device, this restriction does not exist, all capacitors are prepared simultaneously at the start of the measurement.

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Subject invention

A device for controlling digital equilibrium devices, containing a source of silver pulses, a balance indicator, triggers, coping schemes and separating elements, characterized in that, in order to simplify the device and speed up, the output of each trigger is connected to the first input of the coincidence circuit, the second input of which connected to the clock bus, and the output through a series-connected rectifier element and a separation element is connected to

the input of the subsequent trigger, and through two series-connected diodes connected; with BUS reset clock.

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