SU1401393A1 - Digital integrating voltmeter - Google Patents

Abstract

This invention relates to electrical measuring technology. The voltmeter contains an integrator 1, a null organ 3, a control unit 4, an interference period generator 5, a start block 6, a controlled generator 12 counting pulses, a key 13, decoupling elements 14 and 15, a counter 16 pulses, a counting block 17 and Shaper 19 "Reset. The introduction of logic block 8, diode-resistor circuits 9 and 10, capacitor 11, block 18 for isolating the last pulse and the formation of new functional connections increase the noise immunity and simplify the design of the voltmeter. 2 Il.

Description

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The invention relates to electrical measuring equipment, in particular to digital integrating voltmeters.

The purpose of the invention is to improve noise immunity and simplify a digital voltmeter.

FIG. 1 shows a functional diagram of a digital integrating voltmeter; in fig. 2 - time diagram of his work.

The digital integrating voltmeter contains an integrator 1, at the input of which a switch 2 is installed, and the output is a null organ 3, a control unit 4, a period generator 5, a start unit 6, a time interval comparison unit 7, a logic unit 8, two diode-resistor circuits 9 and 10, capacitor 11, controlled oscillator 12 counting pulses, key 13, elements 14 and 15, pulse counter 16, reading unit 17, last pulse extraction unit 18, shaper 19 "Reset, input terminal 20 for connecting the source measured signal, terminals 21 and 22 for connecting the sources of the reference signal, terminals 23 for connecting the source of the interference signal, and terminals 24 via the Common bus.

The output of the starting block 6 is connected to the first input of the control unit 4, the output of the zero-organ 3 is connected to the second input of the control unit 4. The output of the pulse counter 16 is connected via an isolation element 15 to the third input of the control unit 4. The first and the second outputs of the control unit 4 are connected to the control inputs of the switch 2, the third output of the control unit 4 is connected to the control input of the unit 13.

The terminal 23 is connected to the input of the generator 5 of the disturbance period, the output of which is south-eastward connected to the first input of the time interval comparison unit 7 and to the input of the start-up unit 6. The second input of the time interval comparison unit 7 is connected to the third input of the unit 4 (through the disconnecting element 15 it is connected to the output of the pulse counter 16). ; The output of the time interval comparison unit 7 is connected to the input of the logic unit 8, the first output of which is connected via a diode-resistor circuit 9 to a capacitor 11 connected between the control input of the generator 12 and the common bus. The second output of logic unit 8 via diode-resistor circuit 10 is also connected to capacitor 11. Generator 12 output via key 13 and isolation element 14 is connected to the input of counter 16 and to the input of block 18 for the extraction of the last pulse, the output of which is connected to the input of the rotator nineteen.

The information outputs / of the reader 16 are connected to the information inputs :: of the counter block 17, the input “Record of which is connected to the first output of the former 19. The input“ Reset of the counter 16 is connected with the iBTOpbiM output of the former 19.

The presence of block 17 in a digital voltmeter is not necessary in principle, since information on the measurement result can be captured as a code directly from the outputs of the pulse counter 16 and entered, for example, in a computer. In this case, the signal “Record of block 19.

Digital integrating voltmeter works as follows.

Terminal 20 is supplied with a measured signal in the form of a DC voltage with superimposed AC noise. Voltage is supplied to terminal 21

5 of the source of positive polarity, to terminal 22 - the voltage of the reference source of negative polarity. Terminal 23 is supplied with an alternating current voltage, the frequency of which coincides with the frequency of the interference signal (as a rule, it is connected to the supply voltage). At the output of the former 5, square-shaped pulses appear, the frequency of which is a multiple of the frequency of the signal on terminal 23. The trigger unit 6 on the leading edge of the pulse coming from the former 5 generates a trigger pulse arriving at the first input of the control unit 4 (time diagram Fig. 2). On this signal, the block 4 signals the switch 2 with the signal from the first and second outputs, which connects the input signal (terminal 20) to the input of the integrator 1. At the same time, the block 4 opens the key 13 with a signal from the third output, pulses from the generator 12 output through the key 13 and The isolation element 14 begins to arrive at the input of the counter 16. At the moment of replenishment of the pulse counter 16, a signal appears at its output, which passes through the separation element 15 to the third input of the control unit 4. At this moment, unit 4, depending on the signal at the output of the null organ 3 (“O or“ 1), signals the first and second outputs to open the key in switch 2, disconnecting terminal 20 from the input of the integrator I and closing the other key in switch 2, connecting one of the terminals 21 or 22 (depending on the state

5 null-organ 3), thereby connecting one of the sources of the reference voltage to the input of the integrator 1. The integrator 1 begins to discharge and when the output voltage of the integrator reaches zero level, the zero-state state 3 changes,

0 ie the signal at its output changes from "O to" 1 or vice versa. At this moment, unit 4 opens the key 13 with a signal from the third output and the number of pulses in the counter 16 pulses is proportional to the value of the measured signal. Besides,

5, unit 4 sets switch 2 to a state in which the input of integrator 1 is closed with terminal 24 (common bus). The control unit 4 may be supplied

An additional logic circuit, which, depending on the polarity of the reference signal source connected in the second measurement cycle, indicates the polarity sign of the measured signal. In this part, the operation of the voltmeter does not differ from the operation of the known device.

At the moment of termination of the pulse packet at the input of the counter 16 (at the moment of closing the key 13) at the output of the block 18, the signal "1 changes to" O.

The output signal of the block 18 is fed to the input of the imager 19 (Fig. 2), which produces two time-shifted pulses, one at the output "Record, the other at the output" Reset (Fig. 2). The "Record" pulse is fed to the "Record of the memory register of block 17" input and rewrites the measurement result from the counter 16 pulses into its memory register. After that, the signal "Reset block 19 is fed to the input" Reset counter 16 and translates the counter to the zero position. The measurement result, recorded as a code in the memory register of block 17, is displayed on the digital indicator of block 17.

Simultaneously with the described processes, the signal from the output of the imaging unit 5, the duration of which is equal to or a multiple of the duration of the interference period, goes to the first input of the time interval comparison unit 7, to the second input of which a signal comes from the output of counter 16 (through the element 15).

The signal from the output of block 7 is fed to the input of the logical block 8 ,. the sync input of which receives a signal from the control input of the key 13. If the sync input of block 8 is "1 (key 13 open), and the input of logical block 8 is signal" 1 (frequency is lower than the required value), then the first output of block 8 A “1” signal is generated, and at the second output, a “O” signal. These signals do not affect the capacitor 11 due to the appropriate inclusion of diodes of diode-resistor circuits 9 and 10.

At the moment of occurrence, the signal "O (key 13 closed)" does not change at the first output of block 8 at the synchronization input of block 8, and the signal "1 is generated at the second output and is equal in duration to the duration of signal" O at the sync input of the device. This "1" signal passes through the diode resistor circuit 10 and changes the voltage on the capacitor 11 upwards. An increase in the voltage across the capacitor I leads to an increase in the frequency of the Generator 12, since an increase in the voltage on the varicap (at the control input of the generator 12) leads to a decrease in the capacity of the varicap.

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If the signal "O (frequency higher than the required value) appears at the next clock cycles at the input of logic block 8, then at the second output of block 8 the signal is" O ", and at the first output during the duration of the zero signal at the clock input the signal is equal to" O , and the rest of the time - “b. The signal "O on the second output of block 8 does not affect the voltage of capacitor 11 due to the large reverse resistance of the diode-resistor circuit 10, and during the duration of the signal" O on the first output of block 8, the voltage on capacitor 11 decreases due to discharge through the diode a resistor circuit 9. Therefore, the frequency of the generator 12 is reduced. Thus, an automatic adjustment of the frequency of the generator 12 to the frequency of the disturbance is ensured, and thus the noise immunity of the voltmeter is high.

Claims (1)

Invention Formula A digital integrating voltmeter containing an integrator with an input switch and a zero-body at the output, a control unit, a start-up unit, a controlled pulse generator with a key at the output, a pulse counter, the input of which is connected to the output of the key through an isolator, shaper "Reset," the output of which is connected to the thickness "Reset of the pulse counter, the inputs of the control unit are connected respectively to the output of the trigger unit, to the output of the zero organ and through the second isolator to the output of the pulse counter The outputs of the control unit are connected respectively to the control inputs of the switch controlling the key input, characterized in that, in order to increase the noise immunity while simplifying the device, it is equipped with a time interval comparison unit, a logic unit, two diode-resistor circuits, the capacitor, the last pulse separation unit, one of the inputs of the time interval comparison block is connected to the output of the period generator; the second input of the time interval comparison block through the second element CBA dressing connected to the output of the pulse counter, the output of unit comparison interval. the time shafts are connected to the input of the logic unit, the clock input of which is connected to the control input of the key, the outputs of the logic unit are connected to the capacitor connected to the control input of the controlled pulse generator through the corresponding diode-resistor circuit between the input of the pulse counter and the input shaper “Reset the input of the launcher is connected to the output of the shaper of the period of interference. block 5 Blonb flea 1b Block 18 Block 19., add up Block 19 Reset Block 16 Block BLYKD i