JPH0553353B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a countdown type synchronization signal generation device for a television receiver, and particularly to a synchronization signal generation device suitable for integration into an IC (integrated circuit). . (b) Prior art In a television receiver, a signal with a frequency _nH , which is an integral multiple of the horizontal frequency _H , is generated in synchronization with a horizontal synchronization signal, and this signal is divided according to the vertical synchronization signal to obtain a signal with a vertical frequency _V. A vertical deflection circuit is known that uses this signal to perform vertical deflection. An example of converting such a circuit into an IC (integrated circuit) is ''
85 Sanyo Semiconductor Handbook Monolithic Bipolar Integrated Circuits Edition” (published March 20, 1985) No. 1000
IC LA7620 for video, color, and deflection circuits shown on page
There is. FIG. 2 shows a circuit in which the synchronous signal generator portion is extracted from the IC. In Figure 2, 1 is
The video signal from the video detection circuit (not shown) is sent to the composite sync separation circuit 3 via input pin 2.
and separates composite synchronization signals such as horizontal and vertical synchronization signals. Since the composite synchronization signal is applied to the vertical synchronization separation circuit 7 consisting of an integrating circuit 4, a clamp circuit 5 , and a transistor 6, a pulse signal synchronized with the vertical synchronization signal can be obtained at the collector of the transistor 6, and the pulse The signal is applied to frequency divider circuit 8 as a reset signal. On the other hand, the signal generation circuit 9 to which the composite synchronization signal obtained from the composite synchronization separation circuit 3 is applied has a frequency twice the horizontal frequency _H synchronized with the horizontal synchronization signal.
_2H signal is generated, and this signal is applied to the frequency dividing circuit 8 as a clock signal. Therefore, the frequency dividing circuit 8 divides the frequency of the _2H signal into 1/525 in accordance with the pulse from the vertical synchronization separation circuit 7.
As a result, an output signal of vertical frequency _V from the frequency dividing circuit 8 is applied to the base of the output transistor 10, and a driving pulse for driving the vertical deflection circuit 12 can be obtained at the output pin 11. Therefore, according to the circuit shown in FIG. 2, a driving pulse for vertical deflection can be obtained from the video signal. (c) Problems to be Solved by the Invention When inspecting the frequency division operation of the frequency divider circuit 8 inside the IC 1 in the circuit shown in FIG. All you have to do is observe. However, in order to know whether or not the vertical driving pulses are being generated in a correct counting operation, it is necessary to check the intervals of the vertical driving pulses, which is a problem in that it is time consuming. (d) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and includes an output transistor to which an output signal of a frequency dividing circuit is applied and which generates a vertical drive pulse at its output terminal; A bias circuit for applying a bias voltage to the base of the output transistor; and means for controlling the bias circuit and changing the output bias voltage of the bias circuit when the frequency dividing circuit performs a predetermined count. Features. (E) Effect According to the present invention, when the frequency dividing circuit performs a predetermined count, the voltage obtained at the output terminal of the output transistor is changed in the opposite direction to the vertical drive pulse, so that the output terminal By observing the signal waveform generated in the above, it is possible to easily check whether or not the frequency dividing circuit is operating normally. (F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention.
Reference numeral 13 denotes a first circuit to which a composite synchronization signal from the composite synchronization separation circuit 3 is applied to the base to perform a switching operation.
The emitters of transistors 14 to 16 are resistors 1
The first to third constant current transistors are respectively connected to the power supply +Vcc via 7 to 19, 20 is a diode to which a constant current is supplied from the first and second constant current transistors 14 and 15, and 21 is a diode connected to the collector. 3 A second transistor to which a constant current is supplied from the constant current transistor 16 and whose base is connected to the collector of the first transistor 13; 22 is a charging/discharging capacitor that is charged and discharged by turning on and off the second transistor 21; 23 is a positive A comparator circuit has one end of a charging/discharging capacitor 22 connected to its input terminal and a reference power supply connected to its negative input terminal, and 24 has a base to which the first divided output of the frequency dividing circuit 8 is applied, and an emitter which is grounded. A third transistor 25 is a fourth transistor to which the second frequency divided output of the frequency dividing circuit 8 is applied to the base and whose emitter is grounded; 26 is a resistor 27, 28, and 29 and a diode 30, 31;
and a bias circuit for temperature compensation consisting of 32;
33 is an output transistor whose base is connected to the bias circuit 26 , whose collector is connected to the power supply via a diode 34 and a resistor 35, and whose emitter is connected via the output pin 11 to an external variable resistor 36 serving as a load. It is. In addition, diode 34
are the first to third constant current transistors 14 to 16
and are connected in a current mirror relationship of 1:1/m (where m≧1). Also, in Figure 1, the second
Circuit elements that are the same as those in the figures are given the same reference numerals, and their explanations will be omitted. In FIG. 1, a composite synchronization signal as shown in FIG. 3A can be extracted from the video signal applied to the composite synchronization separation circuit 3 via the input pin 2. The composite synchronization signal is applied to the signal generation circuit 9 and to the base of the first transistor 13. When a rectangular pulse corresponding to the vertical drive pulse is applied to the base of the first transistor 13, the first transistor 13
is turned on and the second transistor 21 is turned off, so that the charging/discharging capacitor 22 is constantly charged with the current I _O by the third constant current transistor 16, and its terminal voltage is applied to the positive input terminal of the comparator circuit 23. When the rectangular pulse is no longer applied to the base of the first transistor 13, the first transistor 13 is turned off and the second transistor 21 is turned on. Since the diode 20 and the second transistor 21 have a current mirror circuit configuration, when a current 2IO, which is the sum of the currents _IO of the first and second constant current transistors 14 and 15, flows through the diode ₂₀ , the second transistor 21 , the third constant current transistor 16
A current 2I _O which is the sum of the current I _O and the discharge current I _O of the charging/discharging capacitor 22 flows. Therefore, when a composite synchronizing signal as shown in FIG. 3A is applied to the base of the first transistor 13, an output signal of the charging/discharging capacitor 22 as shown in FIG. 3B is applied to the positive input terminal of the comparison circuit 23. Ru. Here, if the voltage of the reference power supply of the comparator circuit 23 is set as shown in the dashed line in FIG.
3 is applied to the frequency divider circuit 8 as a reset signal. Incidentally, the frequency dividing circuit 8 has a circuit configuration as shown in FIG. A pulse with a frequency of 2 _H supplied to the clock terminal
The frequency is divided by a frequency divider consisting of . When the 512th (256H) Hth (512th) input pulse is counted after the frequency divider is reset, the 10th T
-Q output of FF46 becomes "H" level. The "H" level signal is applied to one input of the NAND circuit 47. As a result, while the output of the 10th T-FF 46 is at the "H" level, an inverted signal of the Q output of the 4th T-FF 40 is generated at point C as the second frequency-divided output. Therefore, the signal generated at point C has a period of 8H (where H represents one period of the horizontal synchronizing signal). Also, when a reset pulse is applied to reset terminal A, the first SR-FF48 is set and its Q
The output is applied to the D-FF 50 via the NOR circuit 49. On the other hand, since the C terminal of the D-FF50 is connected to the clock terminal is applied to the frequency divider as Further, since the Q output is applied to the set input of the second SR-FF 52 via the inverter 51, an output pulse, which is the first frequency-divided output, is generated at point B. Furthermore, the 2nd SR-FF
52 is reset after the frequency divider is reset and when 8H is counted, the Q output becomes "L" again.
level. Therefore, an output pulse of 8.5H is generated at point B. In addition, when the reset signal is not applied to the reset terminal at point A, when the frequency divider counts 296H, all the inputs of the AND circuit 53 become "H" level,
The output becomes "H" level and triggers the D-FF50. As a result, the frequency divider is reset and the second SR-FF 52 is set to generate an output pulse at point B. Therefore, 2nd SR-FF5
2 is set by the reset signal applied to point A or the output signal of AND circuit 53. Returning to Figure 1 again, in the case of NTSC system
A vertical synchronization signal arrives at a cycle of 262.5H. Since the frequency dividing circuit 8 has the configuration and operation as described above, the second frequency divided output generated from the point C of the frequency dividing circuit 8 is at the "H" level until 260H, and thereafter goes "L" and "H" every 4H. Repeat. Therefore, the fourth transistor 25 is turned on when the second frequency-divided output is at "H" level, and the resistor 29 and diode 32 of the bias circuit 26 are turned on.
to shoot. As a result, the voltage at point D becomes the first predetermined value, and the resistors 27, 28, and 29
Assuming that all values of are equal, the output transistor 3
The emitter voltage of No. 3 is 1/2Vcc. When the frequency dividing circuit 8 counts up to 260H, the second frequency divided output of the frequency dividing circuit 8 becomes "L" level, and the fourth transistor 25 is turned off. As a result, the voltage at point D becomes the second
becomes a predetermined value, and the emitter voltage of the output transistor 33 becomes 2/3 Vcc. Next, at 261.5H, a vertical synchronizing signal as shown in Figure 3 (c) is applied from point A to the frequency divider circuit 8, and at 262H, a reset occurs and the third transistor 24 is turned on by the first frequency division output from point B. , the emitter voltage of the output transistor 33 becomes the ground potential. Further, the first frequency-divided output from point B turns off the third transistor 24 after 8.5H, so the emitter voltage of the output transistor 33 becomes 1/2 Vcc again. As a result, the output voltage waveform at the emitter of the output transistor 33 becomes as shown in FIG. 4A. Furthermore, if the vertical synchronizing signal is not applied to point A, the second frequency-divided output from point C of the frequency divider circuit 8 is inverted every 4H after 260H, so the emitter voltage of the output transistor 33 becomes 1/2Vcc. 2/3Vcc is repeated in 4H cycles, and reset occurs at 296H.
At 296.5H, the third transistor 24 is turned on by the first frequency-divided output from point B, and the output transistor 33 is turned on.
The emitter voltage of is at ground potential. As a result,
The output voltage waveform at the emitter of the output transistor 33 is as shown in FIG. 4B. In this way, if the frequency divider circuit 8 is operating correctly, when a normal video signal is applied to the input pin 2, the output voltage waveform shown in Figure 4A will be generated at the output pin 11, and the video signal When not applied to input pin 2, the self-resetting function of frequency divider circuit 8 causes the fourth
Since the output voltage waveform shown in FIG. 9 is generated at the output pin 11, the operation of the frequency divider circuit 8 inside the IC 1 can be easily inspected. On the other hand, as is clear from FIG. 4A and FIG.
If the value of 6 is R _O , the current flowing through the output transistor 33 is Vcc/2R _O during normal times, and 2Vcc/3R _O during the period when the vertical synchronization signal is expected to arrive. Since the current flowing through the emitter and collector of the output transistor 33 can be considered to be equal, the first to third constant current transistors 14 to 16, which are in a current mirror relationship with the diode 34, have currents of Vcc/2mR _O and 2Vcc/3mR _O. flows. Therefore, when the current is 2Vcc/3mR _O , the charging current to the charge/discharge capacitor 22 is
This is larger than when Vcc/2mR _O , and the detection sensitivity of the vertical synchronization signal can be increased when necessary, allowing highly accurate detection even in the case of a weak electric field. (G) Effects of the Invention As described above, according to the present invention, a vertical drive pulse and a waveform indicating the operating state of the frequency divider circuit can be obtained at the output terminal of the output transistor, so the function of the frequency divider circuit inside the IC can be simplified. In addition to being able to perform tests, a special test pin is not required for the test, so it is possible to provide a synchronization signal generator suitable for IC implementation.
In addition, if the vertical synchronization signal is detected by switching the detection sensitivity according to the output signal generated at the emitter of the output transistor as in the embodiment, even if the level of the vertical synchronization signal decreases in a weak electric field, etc., it can be detected sufficiently. It can be performed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional synchronization signal generator, FIG. 3 is a waveform diagram showing how a composite synchronization signal becomes a reset signal, and FIG. FIG. 4 is a waveform diagram showing the output waveform generated at the output pin 11, and FIG. 5 is a circuit diagram showing the configuration of the frequency dividing circuit of FIG. 1. 8... Frequency dividing circuit, 24... Third transistor,
25... Fourth transistor, 26 ... Bias circuit, 33... Output transistor.

Claims (1)

[Claims] 1. Using a frequency divider circuit in which a signal corresponding to a vertical synchronizing signal in a video signal is applied as a reset signal, and a signal corresponding to a horizontal synchronizing signal in the video signal is applied as a clock signal. , in a countdown type synchronization signal generation device that generates a control signal and a vertical drive pulse whose level changes at a predetermined cycle when the frequency dividing circuit counts up to the timing when the vertical synchronization signal is expected to arrive; an output transistor that generates the vertical drive pulse and the control signal at one end; a bias circuit that applies a bias voltage to the base of the output transistor; and the frequency divider circuit that is connected to the base of the output transistor via the bias circuit. a first means for changing the output bias voltage of the bias circuit to a first level that is higher or lower than when there is no signal, when the vertical drive pulse and the control signal are not generated, in response to a vertical drive pulse from; A second circuit connected to the base of the output transistor via a bias circuit and controlling the bias circuit according to a control signal to change the output bias voltage of the bias circuit to a second level that is smaller or larger than when there is no signal. means, when the first means selects the large first level, the second means selects the small second level, and the first means selects the small second level; 2. A synchronizing signal generating device, characterized in that when the first small level is selected, the second means selects the second large level.