JPS62247679A - Synchronizing signal generator - Google Patents

Synchronizing signal generator

Info

Publication number
JPS62247679A
JPS62247679A JP61090584A JP9058486A JPS62247679A JP S62247679 A JPS62247679 A JP S62247679A JP 61090584 A JP61090584 A JP 61090584A JP 9058486 A JP9058486 A JP 9058486A JP S62247679 A JPS62247679 A JP S62247679A
Authority
JP
Japan
Prior art keywords
signal
circuit
output
transistor
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61090584A
Other languages
Japanese (ja)
Other versions
JPH0553353B2 (en
Inventor
Hiroyasu Kishi
岸　博泰
Hiromi Arai
新井　洋実
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP61090584A priority Critical patent/JPS62247679A/en
Priority to EP87902721A priority patent/EP0269741B1/en
Priority to PCT/JP1987/000230 priority patent/WO1987006414A1/en
Priority to DE87902721T priority patent/DE3787619T2/en
Priority to US07/141,359 priority patent/US4789896A/en
Priority to KR1019870003693A priority patent/KR930003564B1/en
Publication of JPS62247679A publication Critical patent/JPS62247679A/en
Publication of JPH0553353B2 publication Critical patent/JPH0553353B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)

Abstract

PURPOSE:To simply check the function of a frequency dividing circuit in an IC by changing the output voltage of an output transistor in the direction opposite to the vertical drive pulse when the frequency dividing circuit performs a prescribed counting action. CONSTITUTION:A composite synchronizing signal is extracted out of the video signal applied to an input pin 2 by a composite synchronizing separator 3. Then the composite synchronizing signal is applied to a signal generating circuit 9 for the reduction of a clock of 2fH and also applied to the base of a transistor 13. While a waveform obtained by integrating the composite synchronizing signal is applied to the input of a comparator 23 and a reset pulse is delivered from the comparator 23 in response to a vertical synchronizing signal. A frequency divider 8 counts the clock pulses of 2fH received from the circuit 9 and the output voltage waveform produced at the output pin 11 of an IC varies in response to the working state of the frequency divider 8. Thus the working state of the frequency dividing circuit can be simply checked.

Description

【発明の詳細な説明】 （イ）産業上の利用分野 本発明は、テレビジョン受像機におけるカウントダウン
方式の同期信号発生装置に関するもので、特にＩＣ（集
積回路）化に適した同期信号発生装置に関する。Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a countdown type synchronization signal generation device for a television receiver, and particularly to a synchronization signal generation device suitable for integration into an IC (integrated circuit). .

く口）従来の技術 テレビジョン受像機において、水平同期信号に同期して
水平周波数ｆ１４の整数倍の周波数ｎｆ１４の信号を作
り、これを垂直同期信号に応じて分周して垂直周波数ｆ
ｖの信号とし、この信号を用いて垂直偏向を行う垂直偏
向回路が知られている。その様な回路をＩＣ（集積回路
）化した例としては、”８５三洋半導体ハンドブックモ
ノリシックバイボーラ集積回路編」（昭和６０年３月２
０日発行）第１０００頁に示される映像・色・偏向回路
用ＩＣＬＡ７６２０がある。前記ＩＣから同期信号発生
装置部分を抽出した回路を第２図に示す。第２図におい
て（１）はＩＣであり、映像検波回路（図示せず）から
の映像信号は入力ビン（２）を介して複合同期分離回路
（３）に印加され、水平及び垂直同期信号等の複合同期
信号が分離される。該複合同期信号は積分回路（４）、
クランプ回路（り及びトランジスタ（６）とから成る垂
直同期分離回路（Ｚ）に印加される為、トランジスタ（
６）のコレクタに垂直同期信号に同期したパルス信号を
得ることができ、該パルス信号がリセット信号として分
周回路（８）に印加される。(Example) Conventional technology In a television receiver, a signal with a frequency nf14, which is an integral multiple of the horizontal frequency f14, is generated in synchronization with a horizontal synchronizing signal, and this signal is frequency-divided according to a vertical synchronizing signal to obtain a vertical frequency f14.
A vertical deflection circuit is known that uses a signal of V and performs vertical deflection using this signal. An example of converting such a circuit into an IC (integrated circuit) is "85 Sanyo Semiconductor Handbook Monolithic Bibolar Integrated Circuit Edition" (March 2, 1985).
There is an ICLA7620 for video/color/deflection circuits shown on page 1000 (published on 0). FIG. 2 shows a circuit in which the synchronous signal generator portion is extracted from the IC. In Fig. 2, (1) is an IC, and a video signal from a video detection circuit (not shown) is applied to a composite sync separation circuit (3) via an input bin (2), and horizontal and vertical sync signals etc. composite synchronization signals are separated. The composite synchronization signal is transmitted through an integrating circuit (4),
Since the voltage is applied to the vertical synchronization separation circuit (Z) consisting of the clamp circuit (RI) and the transistor (6), the transistor (
A pulse signal synchronized with the vertical synchronizing signal can be obtained at the collector of 6), and the pulse signal is applied as a reset signal to the frequency dividing circuit (8).

一方、前記複合同期分離回路（３）から得られる複合同
期信号が印加きれる信号発生回路（９）は、水平同期信
号に同期した水平周波数ｆ□の２倍の周波数２ｒＨの信
号を発生し、該信号はクロック信号として前記分周回路
（８）に印加きれる。このため、前記分周回路り８）は
前記２ｆ’ｏの信号を垂直同期分離回路（Ｚ）からのパ
ルスに応じて５２５分の１に分周する。その結果、前記
分周回路（８）から垂直周波数ｆ’ｖの出力信号が、出
力トランジスタ（１０）にベースされ、出力ピン（１１
）に垂直偏向回路（１２）を駆動するための駆動パルス
を得ることができる。On the other hand, the signal generation circuit (9) to which the composite synchronization signal obtained from the composite synchronization separation circuit (3) is applied generates a signal with a frequency of 2rH, which is twice the horizontal frequency f□ synchronized with the horizontal synchronization signal. The signal can be applied to the frequency divider circuit (8) as a clock signal. Therefore, the frequency dividing circuit 8) divides the frequency of the 2f'o signal into 1/525 in response to the pulse from the vertical synchronization separation circuit (Z). As a result, the output signal of the vertical frequency f'v from the frequency dividing circuit (8) is based on the output transistor (10), and the output signal at the output pin (11
) can provide a drive pulse for driving the vertical deflection circuit (12).

従って、第２図の回路によれば映像信号中から垂直偏向
のための駆動パルスを得ることができる。Therefore, according to the circuit shown in FIG. 2, a driving pulse for vertical deflection can be obtained from the video signal.

（ハ）発明が解決しようとする問題点 第２図の回路においてＩＣ（１）内部の例えば、分周回
路（８）の分周力作を検査をする場合には、出力ビン（
１１）に発生する垂直駆動パルスの波形を観測すれば良
い。しかしながら、正しいカウント動作で前記垂直駆動
パルスが発生されているか否かを知るためには前記垂直
駆動パルスの間隔を検査しなければならず、手間がかか
るという問題があった。(c) Problems to be Solved by the Invention In the circuit shown in FIG.
It is sufficient to observe the waveform of the vertical drive pulse generated in step 11). However, in order to know whether or not the vertical driving pulses are being generated in a correct counting operation, it is necessary to check the intervals of the vertical driving pulses, which is a problem in that it is time-consuming.

（ニ）問題点を解決するための手段 本発明は、上述の点に鑑み成されたもので、分周回路の
出力信号が印加され、出力端に垂直駆動パルスを発生す
る出力トランジスタと、該出力トランジスタのベースに
バイアス電圧を印加するバイアス回路と、前記分周回路
が所定のカウントを行ったとき、前記バイアス回路を制
御し、該バイアス回路の出力バイアス電圧を変化させる
手段とを備えることを特徴とする。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and includes an output transistor to which an output signal of a frequency dividing circuit is applied and which generates a vertical drive pulse at the output terminal; A bias circuit for applying a bias voltage to the base of the output transistor; and means for controlling the bias circuit and changing the output bias voltage of the bias circuit when the frequency dividing circuit performs a predetermined count. Features.

（ホ）作用 本発明によれば、分周回路が所定のカウントを行ったと
き、出力トランジスタの出力端に得られる電圧を垂直駆
動パルスと逆方向に変化させる様にしているので、前記
出力端に発生する信号波形を観測することで、前記分周
回路が正常に動作しているか否かを簡単に確認すること
ができる。(e) Effect According to the present invention, when the frequency dividing circuit performs a predetermined count, the voltage obtained at the output terminal of the output transistor is changed in the opposite direction to the vertical drive pulse, so that the output terminal By observing the signal waveform generated in the above, it is possible to easily check whether or not the frequency dividing circuit is operating normally.

（へ〉実施例 第１図は、本発明の一実施例を示す回路図で、（１３）
は複合同期分離回路（３）からの複合同期信号がベース
に印加され、スイッチング動作を行う第１トランジスタ
、（１４）乃至（１６）はエミッタが抵抗（１７）乃至
（１９）を介して各々電源（＋Ｖｃｃ）に接読されてい
る第１乃至第３定電流トランジスタ、（２ｏ）は第１及
び第２定電流トランジスタ（１４）及び（１５）から定
電流が供給されるダイオード、（２１）はコレクタに第
３定電流トランジスタ（１６）から定電流が供給され、
ベースが第１トランジスタ（１３）のコレクタと接続さ
れている第２トランジスタ、（２２）は該第２トランジ
スタ（２１）のオンオフにより充放電を行う充放電コン
デンサ、（２３）は正入力端子に充放電コンデンサ（２
２〉の一端が接続され、負入力端子に基準電源が接続さ
れた比較回路、（２４）は分周回路（８）の第１分周出
力がベースに印加され、エミッタが接地されている第３
トランジスタ、（２５）は分周回路（８）の第２分周出
力がベースに印加され、エミッタが接地きれている第４
トランジスタ、（翻）は抵抗（２７）、（２８）及びり
２９〉とダイオード（３０）、（３１）及び（３２）と
から成る温度補償用のバイアス回路、（３３）はベース
がバイアス回路（翻）に接続され、コレクタがダイオー
ド（３４）及び抵抗（３５）を介して電源に接続され、
エミッタが出力ピン（１１）を介して負荷となる外付け
の可変抵抗（３６）に接続されている出力トランジスタ
である。尚、ダイオード（３４）は第１乃至第３定電流
トランジスタ（１４）乃至（１６）と１：止、（ただし
、ｍ≧１）のカレントミラー関係に接続されている。又
、第１図において第２図と同一の回路素子については、
同一の符号を付し、その説明を省略する。(f> Example) FIG. 1 is a circuit diagram showing an example of the present invention, (13)
are the first transistors to which a composite synchronous signal from the composite synchronous separation circuit (3) is applied to their bases and perform switching operations; The first to third constant current transistors are read directly to (+Vcc), (2o) is a diode to which constant current is supplied from the first and second constant current transistors (14) and (15), and (21) is A constant current is supplied to the collector from a third constant current transistor (16),
A second transistor whose base is connected to the collector of the first transistor (13), (22) a charging/discharging capacitor that charges and discharges by turning on and off the second transistor (21), and (23) charging a positive input terminal. Discharge capacitor (2
2> is connected to one end, and the reference power supply is connected to the negative input terminal of the comparator circuit. (24) is the comparator circuit to which the first frequency division output of the frequency divider circuit (8) is applied to the base and the emitter is grounded. 3
The transistor (25) is a fourth transistor whose base is applied with the second divided output of the frequency divider circuit (8) and whose emitter is grounded.
Transistor (transistor) is a bias circuit for temperature compensation consisting of resistors (27), (28) and diode (29) and diodes (30), (31) and (32), and (33) is a bias circuit whose base is the collector is connected to the power supply via the diode (34) and the resistor (35),
This is an output transistor whose emitter is connected to an external variable resistor (36) serving as a load via an output pin (11). Note that the diode (34) is connected to the first to third constant current transistors (14) to (16) in a current mirror relationship of 1:stop (however, m≧1). In addition, regarding the same circuit elements in FIG. 1 as in FIG. 2,
The same reference numerals are given, and the explanation thereof will be omitted.

第１図において、入力ビン（２）を介して複合同期分離
回路（３）に印加される映像信号中からは第３図（イ）
の如き複合同期信号が取り出せる。該複合同期信号は信
号発生回路（９）に印加されると共に第１トランジスタ
（１３）のベースに印加される。In Fig. 1, from among the video signals applied to the composite sync separation circuit (3) via the input bin (2), the signal shown in Fig. 3 (A) is
Composite synchronization signals such as can be extracted. The composite synchronization signal is applied to the signal generation circuit (9) and to the base of the first transistor (13).

第１トランジスタ（１３）のベースに垂直駆動パルスに
応じた矩形パルスが印加跡れると第１トランジスタ（１
３）はオンし、第２トランジスタ（２１）がオフするの
で、充放電コンデンサ（２２）は第３定電流トランジス
タ（１６）により電流１．で定電流充電され、その端子
電圧が比較回路（２３）の正入力端子に印加される。第
１トランジスタ（１３〉のベースに矩形パルスが印加さ
れなくなると、第１トランジスタ（１３）はオフし、第
２トランジスタ（２１）がオンする。ダイオード（２０
）と第２トランジスタ（２１）はカレントミラー回路の
構成になるので、ダイオード＜２０）に第１及び第２定
電流トランジスタ（１４）及び（１５）の電流Ｉゆが加
算された電流２工。が流れると、第２トランジスタ（２
１）には、第３定電流トランジスタク１６）の電流１．
と充放電コンデンサ（２２）の放電電流工。とが加算さ
れた電流２１．が流れる。従って、第１トランジスタ（
１３）のベースに第３図（イ）の如き複合同期信号が印
加されると、比較回路り２３）の正入力端子には第３図
（ロ）の如き充放電コンデンサ（２２）の出力信号が印
加きれる。ここで、比較回路（２３）の基準電源の電圧
を第３図（ロ）の一点鎖線の如く設定すれば、第３図（
ハ）の如き矩形パルスが、比較回路（２３）から分周回
路＜８）にリセット信号として印加される。When a rectangular pulse corresponding to the vertical drive pulse is applied to the base of the first transistor (13), the first transistor (13)
3) is turned on and the second transistor (21) is turned off, so that the charging/discharging capacitor (22) receives a current of 1.3 by the third constant current transistor (16). It is charged with a constant current at , and its terminal voltage is applied to the positive input terminal of the comparator circuit (23). When the rectangular pulse is no longer applied to the base of the first transistor (13), the first transistor (13) is turned off and the second transistor (21) is turned on.
) and the second transistor (21) constitute a current mirror circuit, so the current 2 is the sum of the current I of the first and second constant current transistors (14) and (15) to the diode <20). flows, the second transistor (2
1) includes the current 1. of the third constant current transistor 16).
and the discharge current of the charge/discharge capacitor (22). The current 21. flows. Therefore, the first transistor (
When a composite synchronizing signal as shown in Fig. 3 (a) is applied to the base of 13), the output signal of the charging/discharging capacitor (22) as shown in Fig. 3 (b) is applied to the positive input terminal of the comparator circuit 23). can be applied. Here, if the voltage of the reference power supply of the comparator circuit (23) is set as shown in the dashed line in FIG.
A rectangular pulse as shown in c) is applied as a reset signal from the comparator circuit (23) to the frequency divider circuit <8).

ところで、分周回路（８）は第５図の如き回路構成とな
っている。クロック端子Ｘに供給される周波数２ｆ’＆
Ｉのパルスは、縦続接続されている第１乃至第１０Ｔ−
ＦＦ（ＦＦ：フリッププロップ回路）　（３７）乃至（
４６）から成る分周器で分周される。By the way, the frequency dividing circuit (8) has a circuit configuration as shown in FIG. Frequency 2f'& supplied to clock terminal
The pulses of I are connected to the first to tenth T- pulses connected in cascade.
FF (FF: flip-prop circuit) (37) to (
46).

前記分周器がリセットされてから２５６個の入力パルス
がカウントされると第１０　Ｔ−Ｆ　Ｆ（４６）のＱ出
力がｒ　Ｈ、レベルになる。該ｒ’　Ｈ、レベルの信号
はナンド回路（４７）の一方の入力に印加される。その
結果、第１０７−　Ｆ　Ｆ（４６）の出力がｒＨ」レベ
ルの期間中、ｍ４　Ｔ−Ｆ　Ｆ（４０）（７）Ｑ出力の
反転信号が第２分周出力として点Ｃに発生する。従って
、点Ｃに発生する信号は同期８Ｈ（ただし、Ｈは水平同
期信号の１周期を表わす。）と成る。When 256 input pulses are counted after the frequency divider is reset, the Q output of the 10th TFF (46) becomes rH. The r'H level signal is applied to one input of a NAND circuit (47). As a result, during the period when the output of the 107-th F (46) is at the rH level, an inverted signal of the m4 T-F (40) (7) Q output is generated at point C as the second frequency-divided output. Therefore, the signal generated at point C becomes synchronization 8H (where H represents one period of the horizontal synchronization signal).

又、リセット端子Ａにリセットパルスが印加容れると、
第１　Ｓ　Ｒ−Ｆ　Ｆ（４８）がセットされ、そのＱ出
力がノア回路＜４９）を介してＤ−ＦＦ（５０）に印加
される。一方、Ｄ−ＦＦ（５０）のＣ端子はクロック端
子Ｘに接続されているので、ノア回路（４９）の出力が
印加されてから、次のクロックパルスでＱ出力が発生し
、０．５Ｈ遅延されたＱ出力がリセット信号として分周
器に印加される。又、前記Ｑ出力はインバータ（５１）
を介して第２ＳＲ−ＦＦ（５２）のセット入力に印加さ
れるので、点Ｂに第１分周出力である出力パルスが発生
する。尚、第２ＳＲ−ＦＦ（５２）は分周器がリセット
された後、８Ｈカウントするとリセットされるので、Ｑ
出力は再びｒＬ」レベルとなる。従って点Ｂには８．５
Ｈの出力パルスが発生する。Also, when a reset pulse is applied to reset terminal A,
The first SRFF (48) is set, and its Q output is applied to the D-FF (50) via a NOR circuit <49). On the other hand, since the C terminal of the D-FF (50) is connected to the clock terminal The resulting Q output is applied to the frequency divider as a reset signal. Moreover, the Q output is an inverter (51)
Since it is applied to the set input of the second SR-FF (52) via , an output pulse that is the first frequency-divided output is generated at point B. Note that the second SR-FF (52) is reset when 8H is counted after the frequency divider is reset, so the Q
The output becomes rL'' level again. Therefore, point B has 8.5
A high output pulse is generated.

又、点Ａのリセット端子にリセット信号が印加きれない
場合、分周器が２９６Ｈカウントするとアンド回路（５
３）の入力が全てｒ　Ｈ、レベルとなり、その出力が「
Ｈ」レベルとなってＤ−ＦＦ（５０）をトリガーする。Also, if the reset signal cannot be applied to the reset terminal at point A, when the frequency divider counts 296H, the AND circuit (5
3) All inputs are rH, level, and the output is "
H” level and triggers D-FF (50).

その結果、分周器がリセットされるとともに第２　Ｓ　
Ｒ−Ｆ　Ｆ（５２）がセットされ点Ｂに出力パルスを発
生する。従って、第２ＳＲ−ＦＦ（５２）は点Ａに印加
されるリセット信号又はアンド回路（５３）の出力信号
によりセットされることになる。As a result, the frequency divider is reset and the second S
R-FF (52) is set to generate an output pulse at point B. Therefore, the second SR-FF (52) is set by the reset signal applied to point A or the output signal of the AND circuit (53).

再び第１図に戻って、ＮＴＳＣ方式の場合２６２．５周
期で垂直同期信号が到来する０分周回路り８）は前述の
如き構成・動作を行うので、分周回路り８）の点Ｃから
発生する第２分周出力は２６０ＨまでｒＨ」レベル、以
降４　Ｈオキニ’　Ｌ　Ｊ、ｒＨ，を繰り返えす。従っ
て、第４トランジスタ（２５）は前記第２分周出力が「
Ｈ」レベルの時、オンとなりバイアス回路（翻）の抵抗
（２９）及びダイオード（３２）をショートする。この
結果、点ｐの電圧が第１の所定値となり、抵抗（２７）
、抵抗（２８）及び抵抗（２９）の値を全て等しいとす
ると、出力トランジスタ（３３）のエミッタ電圧は’Ｖ
ｃｃとなる。分周回路（８）が２６０Ｈまでカウントす
ると分周回路（８）の第２分周出力はｒＬ」レベルとな
り、第４トランジスタ（２５）がオフとなる。この結果
、点りの電圧が第２の所定値となり、出力トランジスタ
（３３）のエミッタ電圧は”　Ｖ　ｃ　ｃとなる０次に
２６１．５Ｈで第３図（ハ）の如き垂直同期信号が点Ａ
から分周回路（８）に印加されると、２６２Ｈでリセッ
トがかかり点Ｂからの第１分周出力により第３トランジ
スタ（２４〉がオンとなり、出力トランジスタ（３３）
のエミッタ電圧はアース電位となる。更に点Ｂからの第
１分周出力は８．５Ｈ後、第３トランジスタ（２４）を
オフさせるので、出力トランジスタ（３３）のエミッタ
電圧は再び’Ｖｃｃとなる。この結果、出力トランジス
タ（３３）のエミッタの出力電圧波形は第４図（イ）の
如くなる。Returning to FIG. 1 again, in the case of the NTSC system, the 0 frequency divider circuit 8), in which the vertical synchronizing signal arrives at every 262.5 cycles, has the configuration and operation as described above, so the point C of the frequency divider circuit 8) The second frequency-divided output generated from the second frequency division output reaches the rH level up to 260H, and thereafter repeats 4H, rH, and so on. Therefore, the fourth transistor (25) has the second frequency divided output "
When it is at "H" level, it is turned on and short-circuits the resistor (29) and diode (32) of the bias circuit. As a result, the voltage at point p becomes the first predetermined value, and the resistance (27)
, the value of the resistor (28) and the resistor (29) are all equal, then the emitter voltage of the output transistor (33) is 'V
cc. When the frequency dividing circuit (8) counts up to 260H, the second frequency divided output of the frequency dividing circuit (8) becomes rL'' level, and the fourth transistor (25) is turned off. As a result, the voltage at the point becomes the second predetermined value, and the emitter voltage of the output transistor (33) becomes "V c c". At 261.5H, the vertical synchronizing signal as shown in Figure 3 (C) turns on. A
When the voltage is applied to the frequency divider circuit (8), it is reset at 262H, and the first frequency divided output from point B turns on the third transistor (24), and the output transistor (33)
The emitter voltage of is at ground potential. Further, the first frequency-divided output from point B turns off the third transistor (24) after 8.5H, so the emitter voltage of the output transistor (33) becomes 'Vcc again. As a result, the output voltage waveform at the emitter of the output transistor (33) becomes as shown in FIG. 4(a).

又、点Ａに垂直同期信号が印加されない場合は、２６０
Ｈ以降、分周回路（８）の点Ｃからの第２分周出力は４
Ｈ周期で反転するので、出力トランジスタ（３３）のエ
ミッタ電圧は−ＶＣＣと８Ｖ　ｃ　ｃとを４Ｈ周期で繰
り返えし、２９６Ｈでリセットがかかり２９６．５Ｈで
点Ｂからの第１分周出力により第３トランジスタ（２４
）がオンし、出力トランジスタ（３３）のエミッタ電圧
はアース電位となる。Also, if the vertical synchronization signal is not applied to point A, 260
After H, the second frequency division output from point C of the frequency divider circuit (8) is 4
Since it is inverted in the H period, the emitter voltage of the output transistor (33) repeats -VCC and 8V c c in the 4H period, and is reset at 296H and becomes the first frequency divided output from point B at 296.5H. The third transistor (24
) is turned on, and the emitter voltage of the output transistor (33) becomes the ground potential.

この結果、出力トランジスタフ３３）のエミッタの出力
電圧波形は第４図（ロ）の如くなる。As a result, the output voltage waveform at the emitter of the output transistor 33) becomes as shown in FIG. 4(b).

この様に、分周回路（８）が正しく動作しているならば
、正常な映像信号を入力ピン（２）に印加したときは、
第４図（りの出力電圧波形が出力ピン（１１）に生じ、
又、映像信号を入力ピン（２）に印加しない場合には分
周回路（８）の自己リセット機能により第４図（ロ）の
出力電圧波形が出力ピン（１１）に生じるので、ＩＣ（
１）内部の分周回路（８）の動作を簡単に検査すること
ができる。In this way, if the frequency divider circuit (8) is operating correctly, when a normal video signal is applied to the input pin (2),
The output voltage waveform shown in Figure 4 (ri) is generated at the output pin (11),
Moreover, when the video signal is not applied to the input pin (2), the output voltage waveform shown in FIG.
1) The operation of the internal frequency dividing circuit (8) can be easily inspected.

一方、第４図（り及び（ロ）から明らかな如く、出力ト
ランジスタ（３３）のエミッタ電圧は垂直同期信号の到
来が予想される期間に高くなり、可変抵抗（３６）の値
をＲｏとすれば出力トランジスタ（３３）に流れる電流
は通常時はｉとなり、垂直同期信号の到来が予想される
期間は＆となる。出３Ｒ。On the other hand, as is clear from FIGS. 4(R) and (B), the emitter voltage of the output transistor (33) becomes high during the period in which the arrival of the vertical synchronizing signal is expected, and the value of the variable resistor (36) is set to Ro. For example, the current flowing through the output transistor (33) is i during normal times, and & during the period in which the vertical synchronization signal is expected to arrive.Output 3R.

カトランジスタ（３３）のエミッタとコレクタに流れる
電流は等しいと考えて良いので、ダイオード（３４）と
カレントミラー関係にある第１乃至第３定電流トランジ
スタ（１４）乃至（１６）には　ｈ−と　ｍ　Ｒｈ ２■ 一一二りの電流が流れる。その為、電流」ｊ−Ｌ３　ｍ
Ｒｅ　　　　　　　　　　　　　　　　　　　　　　　
３　ｍＲｅの時には充放電コンデンサ（２２）への充電
電流が、電流−に−の時よりも大となり、垂直同期値２
　ｍ　Ｒｅ 号の検出感度を必要時に上げることができ、弱電界時に
も精度の良い検出を行うことができる。Since the current flowing through the emitter and collector of the constant current transistor (33) can be considered to be equal, the first to third constant current transistors (14) to (16), which are in a current mirror relationship with the diode (34), have h- and m Rh 2■ A current of 112 flows. Therefore, the current "j-L3 m
Re
When the current is 3 mRe, the charging current to the charging/discharging capacitor (22) is larger than when the current is -, and the vertical synchronization value is 2.
The detection sensitivity of m Re can be increased when necessary, and accurate detection can be performed even in a weak electric field.

（ト）発明の効果 以上述べた如く本発明によれば、出力トランジスタの出
力端に垂直駆動パルスと分周回路の動作状態を示す波形
が得られるので、ＩＣ内部の分周回路の機能を簡単に検
査することができるとともに、検査に際し格別の検査ピ
ンを必要としないのでＩＣ化に適した同期信号発生装置
を提供できる。又、実施例の如く、出力トランジスタの
エミッタに生ずる出力信号に応じて検出感度を切換えて
垂直同期信号の検出を行えば、弱電界等において垂直同
期信号のレベルが低下しても、十分に検出を行うことが
できる。(G) Effects of the Invention As described above, according to the present invention, a vertical drive pulse and a waveform indicating the operating state of the frequency divider circuit can be obtained at the output terminal of the output transistor, so that the function of the frequency divider circuit inside the IC can be simplified. In addition, since the present invention does not require special test pins during the test, it is possible to provide a synchronization signal generator suitable for IC implementation. In addition, if the vertical synchronization signal is detected by switching the detection sensitivity according to the output signal generated at the emitter of the output transistor as in the embodiment, even if the level of the vertical synchronization signal decreases in a weak electric field etc., it can be detected sufficiently. It can be performed.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の一実施例を示す回路図、第２図は従
来の同期信号発生装置を示す回路図、第３図は複合同期
信号がリセット信号となる様子を示す波形図、第４図は
出力ピン（１１）に発生する出力波形を示す波形図及び
、第５図は第１図の分周回路の構成を示す回路図である
。 （８）・・・分周回路、（２４）・・・第３トランジス
タ、（２５）・・・第４トランジスタ、（２６）・・・
バイアス回路、（３３）・・・出力トランジスタ。 出願人　三洋電機株式会社外１名 代理人　弁理士　西野卓嗣　外１名 第３図 第４図　　　　　　２４／、５Ｎ ａ４／、ｔＨ ２デｔＨ 手続補正書（自発） 昭和６２年４月７　日FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional synchronization signal generator, FIG. 3 is a waveform diagram showing how a composite synchronization signal becomes a reset signal, and FIG. FIG. 4 is a waveform diagram showing the output waveform generated at the output pin (11), and FIG. 5 is a circuit diagram showing the configuration of the frequency dividing circuit of FIG. 1. (8)... Frequency divider circuit, (24)... Third transistor, (25)... Fourth transistor, (26)...
Bias circuit, (33)...output transistor. Applicant Sanyo Electric Co., Ltd. and one other agent Patent attorney Takuji Nishino and one other person Figure 3 Figure 4 24/, 5N a4/, tH 2detH Procedural amendment (voluntary) April 7, 1988

Claims (1)

【特許請求の範囲】[Claims] （１）映像信号中の垂直同期信号に応じた信号がリセッ
ト信号として印加され、前記映像信号中の水平同期信号
に応じた信号がクロック信号として印加される分周回路
を用いて垂直駆動パルスを発生するカウントダウン方式
の同期信号発生装置において、前記分周回路の出力信号
が印加され、出力端に垂直駆動パルスを発生する出力ト
ランジスタと、該出力トランジスタのベースにバイアス
電圧を印加するバイアス回路と、前記分周回路が所定の
カウントを行ったとき、前記バイアス回路を制御し、該
バイアス回路の出力バイアス電圧を変化させる手段とか
ら成り、前記出力トランジスタの出力端における電圧を
前記分周回路のカウント数に応じて切換える様にしたこ
とを特徴とする同期信号発生装置。(1) Vertical drive pulses are generated using a frequency divider circuit in which a signal corresponding to the vertical synchronizing signal in the video signal is applied as a reset signal, and a signal corresponding to the horizontal synchronizing signal in the video signal is applied as a clock signal. A countdown-type synchronization signal generation device includes an output transistor to which the output signal of the frequency dividing circuit is applied and which generates a vertical drive pulse at an output terminal; a bias circuit which applies a bias voltage to the base of the output transistor; means for controlling the bias circuit and changing the output bias voltage of the bias circuit when the frequency divider circuit performs a predetermined count; A synchronous signal generator characterized in that switching is performed according to the number of signals.
JP61090584A 1986-04-14 1986-04-18 Synchronizing signal generator Granted JPS62247679A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP61090584A JPS62247679A (en) 1986-04-18 1986-04-18 Synchronizing signal generator
EP87902721A EP0269741B1 (en) 1986-04-14 1987-04-13 Circuit for generating vertical synchronizing pulses
PCT/JP1987/000230 WO1987006414A1 (en) 1986-04-14 1987-04-13 Circuit for generating vertical synchronizing pulses
DE87902721T DE3787619T2 (en) 1986-04-14 1987-04-13 CIRCUIT TO GENERATE VERTICAL SYNCHRONIZING CURRENTS.
US07/141,359 US4789896A (en) 1986-04-14 1987-04-13 Vertical synchronizing pulse generating circuit
KR1019870003693A KR930003564B1 (en) 1986-04-18 1987-04-17 Synchronizing pulse generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61090584A JPS62247679A (en) 1986-04-18 1986-04-18 Synchronizing signal generator

Publications (2)

Publication Number Publication Date
JPS62247679A true JPS62247679A (en) 1987-10-28
JPH0553353B2 JPH0553353B2 (en) 1993-08-09

Family

ID=14002493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61090584A Granted JPS62247679A (en) 1986-04-14 1986-04-18 Synchronizing signal generator

Country Status (2)

Country Link
JP (1) JPS62247679A (en)
KR (1) KR930003564B1 (en)

Also Published As

Publication number Publication date
KR930003564B1 (en) 1993-05-06
KR870010734A (en) 1987-11-30
JPH0553353B2 (en) 1993-08-09

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