JP3126390B2 - Signal detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal detection circuit for detecting that a dynamic signal has been input from the state of a static signal generated by a switch or the like, and more particularly to a semiconductor device which extends the detection of a dynamic signal to a low frequency band. The present invention relates to a signal detection circuit that can be mounted on an integrated circuit or the like.

[0002]

2. Description of the Related Art Conventionally, as a signal detection circuit of this kind,
There was one as shown in FIG. FIG. 2 is a circuit diagram showing one configuration example of a conventional signal detection circuit. The signal detection circuit 10 is provided between an input signal generation unit 20 mounted on a microcomputer or the like and a counter 30, for example, and detects a pulse-like dynamic signal generated by the input signal generation unit 20 to generate a counter 30. Output function. The counter 30 has a function of detecting the number of dynamic signals from the input signal generator 20 and outputting a count result to a controller (not shown) of the microcomputer. This signal detection circuit 10 has an input terminal 11 for inputting an input signal Si,
The input terminal 11 has a p-channel MOS transistor (hereinafter referred to as pMOS) 1 as an input transistor.
2 gates G are connected. The source S of the pMOS 12 is connected to the positive power supply potential Va, and the drain D is connected to the negative power supply potential Vb via a control node N via a parallel connection of a capacitor 13 and a resistor 14 serving as discharging resistance means. . Further, the input side of the inverter 15 which is a signal output means is connected to the drain D. The output side of the inverter 15 is connected to an output terminal 16 for outputting the output signal So.

The operation of the signal detection circuit 10 will be described with reference to FIGS. FIG. 3 is a voltage waveform diagram of a conventional signal detection circuit, and shows an operation concept relating to input / output. FIG. 4 is a partially enlarged waveform diagram of FIG. Note that V in FIG.
c is a control node N connected to the drain D of the pMOS 12
Is the threshold potential of the inverter 15. When the input signal Si changes from a high level (hereinafter, “H”) stationary signal state to a low level (hereinafter, “L”),
The pMOS 12 is turned on. The charge is rapidly charged in the capacitor 13 through the pMOS 12. pMOS1
2, that is, the potential Vc on the control node N
Rises rapidly. When the potential Vc rises above the threshold potential Vr of the inverter 15, the output signal So of the inverter 15 changes from “H” to “L”.

When the input signal Si changes from "L" to "H", the pMOS 12 is turned off. The electric charge charged in the capacitor 13 is discharged through the resistor 14. The potential Vc on the control node N falls relatively slowly. Potential V
If the input signal Si becomes "L" again while c does not fall below the threshold potential Vr of the inverter 15, the pMOS 12 is turned on and the potential Vc rapidly rises again. The output signal So of the inverter 15 maintains "L", is output to the output terminal 16, and the signal is detected. For example,
While a dynamic signal such as a clock pulse signal is being input, the output signal So of the inverter 15 keeps “L”. When the input signal Si goes to the “H” rest state again, the pMOS 12 is turned off. The charge charged in the capacitor 13 is discharged through the resistor 14, and the potential Vc on the control node N falls. The potential Vc is equal to the threshold potential Vr
Below this, the output signal So of the inverter 15 becomes "H" again. At the output terminal 16, the signal detection is completed, and the state returns to the state before the detection. As described above, it is detected that a dynamic signal has been input from the state of the stationary signal of the input signal Si.

[0005]

However, the signal detection circuit 10 having the above configuration has the following problems. (A) As the frequency of the dynamic signal decreases, the time in which the pMOS 12 is in the off state also increases, and the time required to discharge the charged charge naturally increases. As the discharge time of capacitor 13 becomes longer, potential Vc on control node N falls below threshold potential Vr of inverter 15. When the potential Vc becomes equal to or lower than the threshold potential Vr, the output signal So of the inverter 15 changes from “L” to “H”, causing a malfunction. Essentially, while the dynamic signal is being input, “L” must appear as the output signal So of the inverter 15. (B) To operate in a low frequency band, the capacitor 13
It is necessary to lengthen the discharge time determined by the time constant τ by the resistor 14 and the resistor 14. To increase the time constant τ, the capacitance of the capacitor 13 or the resistance of the resistor 14 may be increased. However, when the signal detection circuit 10 is configured by a monolithic integrated circuit (hereinafter, referred to as a monolithic IC), it is not possible to form the capacitor 13 having several hundred pF or the resistor 14 having several hundred kΩ or more without increasing the circuit forming area. Very difficult. For this reason, the signal detection circuit 10 capable of detecting a signal at a frequency of 100 kHz or less cannot be formed by a monolithic IC. (C) When detection up to a low frequency is required, a configuration in which the capacitor 13 and the resistor 14 are connected outside the monolithic IC is adopted. In this case, there is a problem that the number of terminals of the monolithic IC increases and the manufacturing process becomes complicated. (D) If it is formed in a monolithic IC, the area where the capacitor 13 and the resistor 14 are formed is enlarged. It is extremely difficult to form a large-capacity capacitor 13 and a large-resistance resistor 14 in a limited space of a monolithic IC. An object of the present invention is to increase the number of terminals for externally connecting a resistor or a capacitor when a signal detection circuit capable of detecting a signal up to a low frequency band is configured by a monolithic IC. It is an object of the present invention to provide a signal detection circuit which solves the problem that a large space must be provided when a resistor or a capacitor is formed in a monolithic IC.

[0006]

According to a first aspect of the present invention, there is provided a signal detection circuit, comprising: a first node to which a first power supply potential is applied;
Connected to the node and conducts according to the input signal
An input transistor whose voltage is controlled, and the control node
And a second power supply potential different from the first power supply potential
Connected to a second node provided with
Flows to the control node when the transistor is conducting
The capacitor charged by the current and the base
And the collector is connected to the first node.
A continuous bipolar transistor and the bipolar transistor
Connection between the emitter of the transistor and the second node
Through the bipolar transistor,
A discharge resistance means for discharging the electric charge stored in the capacitor;
Connected to the control node according to the potential of the control node.
Output means for outputting an output signal . In a second aspect based on the first aspect, the discharge resistance means is a first resistance element .
One electrode is connected to the emitter of the bipolar transistor.
A second electrode is connected to the second node,
The input signal is supplied to the control electrode, and the input transistor is
It is a transistor of the opposite conductivity type to the star .

[0007]

According to the first aspect of the present invention, since the signal detection circuit is configured as described above, when the input signal turns on the input transistor, for example, the capacitor is charged by the current flowing to the control node through the input transistor. . At this time, the base emitter of the bipolar transistor
Current also flows to the
Since the current is small, enough charge is stored in the capacitor.
Can be When the input transistor is turned off by an input signal, for example , a new charge is stored in the capacitor.
Since it is not accumulated, the electric charge charged in the capacitor becomes
It is discharged through the control node, between the base and the emitter of the bipolar transistor, and through the discharging resistor. The conduction state of the bipolar transistor is controlled by the current flowing through the control node to the base of the bipolar transistor. The apparent resistance of the control node and the base side of the bipolar transistor viewed from the capacitor increases at a value corresponding to the current amplification factor of the bipolar transistor. Then, the output signal corresponding to the potential of the control node,
Is output from the output means. This makes it possible to accurately detect an input signal up to a low frequency band . No.
In the invention of the second aspect, the discharging resistance means is connected to the input transistor.
Since it is a reverse conductivity type transistor, the input transistor
When the capacitor is charged while the star is on,
The reverse conductivity type transistor is turned off and the bipolar transistor is turned off.
Do not apply current to the base / emitter side of
No. When the input transistor is off, the reverse conductivity type
The transistor is turned on and stored in the capacitor
The charged charge is the base / emitter of the bipolar transistor
And through the transistor of the opposite conductivity type.

[0008]

FIG. 1 is a circuit diagram of a signal detection circuit according to a first embodiment of the present invention. The input signal Si generated by the input signal generator 50 is input to the signal detection circuit 60. The signal detection circuit 60 has a function of detecting the input signal Si and outputting the detected signal to the counter 70. The input signal generator 50, the signal detection circuit 60, and the counter 70 are formed on a semiconductor integrated circuit. The signal detection circuit 60 has an input terminal 61 for inputting an input signal Si, and the input terminal 61 is connected to a gate G of a pMOS 62 which is an input transistor. The source S of the pMOS 62 is supplied with a first power supply potential, ie, a positive power supply potential Va.
Is connected to the node, the drain D via the control node N is connected to the base B of the NPN transistor 64 which is one end N1, and the bipolar transistor of the capacitor 63. The other end N2 of the capacitor 63, the negative power supply potential Vb is connected to the second node receiving a second power supply <br/> potential.

[0009] The collector C of the transistor 64 is connected to a first node which is given a positive power supply potential Va, the emitter E and the second negative power supply potential Vb is applied through a resistor 65 as a discharge resistor means Connected to a node.
The control node N, the input side of the inverter 66 is output means connected to the output side of the inverter 66 is connected to an output terminal 67 for the output signal So.. The inverter 66 is configured by a complementary MOS transistor or the like, and outputs an “H” output signal So at an input voltage equal to or lower than its own threshold voltage Vr, and outputs an “H” output signal So at an input voltage equal to or higher than the threshold voltage Vr.
It has a function of outputting an output signal So of “L”.

FIG. 5 is a circuit diagram of a main part of FIG. Resistance 6
5, the second current flowing through the transistor 64 is i, the first current flowing to the base B of the transistor 64 is ib, and the current amplification factor of the transistor 64 is β. The current i passing through the resistor 65 is the emitter current of the transistor 64. Transistor 6
According to the general characteristic of No. 4, the current ib flowing through the base B is expressed by the equation (1). ib = i / (1 + β) (1) The discharge current flowing through one end N1 of the capacitor 63 and the control node N is the base current ib flowing through the base B of the transistor 64. When the potential of the control node N is Vc and the resistance
Is the resistance value of R, and the voltage between the emitter and the base of the transistor 64 is Vbe, the current i flowing through the resistor 65 is expressed by equation (2). i = (Vc−Vbe) / R (2) The apparent resistance Ro seen from the capacitor 63 is given by the following equation (3).
It is represented by Ro = Vc / ib (3) By substituting equation (1) into equation (3), equation (4) is obtained. Ro = Vc / i · (1 + β) (4) By substituting equation (2) into equation (4), equation (5) is obtained. Ro = Vc / (Vc−Vbe) · R · (1 + β) (5) As apparent from the equation (5), the apparent resistance Ro seen from the capacitor 63 is equal to the resistance R of the resistor 65. About 1
+ Β times. The current amplification factor β of the transistor 64 is usually about 50 to 300. Therefore, the resistance Ro is obtained as an extremely large value which is increased to a value of 51 to 301 times.

As described above, by increasing the apparent resistance Ro at a value corresponding to the current amplification factor β of the transistor 64, signal detection up to a target low frequency band is performed with a small resistance value. That is, a signal can be detected up to a target low frequency band with a small capacitance value or a small resistance value. The operation of the signal detection circuit 60 configured as described above will be described with reference to FIG. FIG. 6 is a voltage waveform diagram of the signal detection circuit 60 according to the first embodiment of the present invention. In the figure, Vc is the potential of the control node N. When the input signal Si is in the quiescent state of “H”, the pMOS 62 is off. The charge of the capacitor 63 is
Through the base B , the emitter E and the resistor 65 to the negative power supply potential Vb. One end N1 of the capacitor 63
Is maintained at “L” close to the negative power supply potential Vb. When the potential Vc is set to a level lower than the threshold voltage Vr of the inverter 66, the output signal So of the inverter 66 becomes “H” and is output from the output terminal 67. When the dynamic input signal Si becomes “L” from this state,
The pMOS 62 is turned on, and the capacitor 63 is rapidly charged through the pMOS 62. At this time,
To the base B, emitter E and resistor 65 side of the transistor 64
Although the current flows, the apparent resistance viewed from the capacitor 63
The anti-Ro is about 1 + β times the resistance value R of the resistor 65.
Flows from the base B of the transistor 64 to the emitter E.
Since the current that flows is extremely small, sufficient
63. Thereby, the capacitor 6
The potential Vc of the control node N on one end N1 side of No. 3 rapidly rises. When the potential Vc rises above the threshold potential Vr of the inverter 66, the output signal So of the inverter 66 changes from “H” to “L”. In this way, an output signal So indicating that the signal has been detected is obtained.

[0012] Then at "H" from the dynamic input signal Si is "L", Ri pMOS62 is Do off, calibration
No new charge is accumulated in the capacitor 63. Therefore, the electric charge charged in the capacitor 63, the transistor 64
Through the base B and the emitter E, the resistance value R of the resistor 65 is obtained.
Is discharged by 1 + beta multiplied by the apparent resistance Ro of the potential Vc of the control node N is very slowly lowered. When the dynamic input signal Si goes low again while the potential Vc does not fall below the threshold potential Vr, the potential Vc of the control node N rapidly rises again, and the output signal So of the inverter 66 goes low. This means that the signal has been detected and maintained. When the input signal Si is in the quiescent state of “H”, p
The MOS 62 is turned off, the charge charged in the capacitor 63 is discharged, and the potential Vc falls. When the potential Vc at this time falls below the threshold potential Vr of the inverter 66, the output of the inverter 66 changes from "L" to "H",
An output signal So corresponding to the potential Vc of the control node N is output to the output terminal 67, and the state returns to the state before signal detection.

The first embodiment has the following advantages. (1) The apparent resistance Ro of the resistance 65 is changed to the transistor 6
4, which can be increased by approximately β times as represented by the current amplification factor β. For this reason, even if the resistance value R of the resistor 65, the capacitance value of the capacitor 63, and the threshold potential Vr of the inverter 66 are the same as the constants of the conventional circuit, the frequency of the dynamic signal handled by the signal detection circuit 60 is substantially A frequency as low as 1 / β can be detected. When the input signal Si having the same frequency as that of the conventional signal detection circuit 10 is detected, the resistance value R
Can be made approximately 1 / β of the value of the conventional circuit. Since the time for discharging the electric charge is determined by the time constant τ of the capacitor 63 and the resistor 65, the capacitance value of the capacitor 63 can be set to a value as small as approximately 1 / β of the conventional circuit. Therefore, the formation area of the resistor 65 and the capacitor 63 can be reduced. (2) The apparent resistance Ro increases by β times. For this reason, it can be realized with a simple configuration using the transistor 64,
It can be easily manufactured in a small space. (3) Since the apparent resistance Ro can be increased by a factor of β, the structure of the resistance 65 can be simplified. The signal detection circuit 60 capable of detecting up to a low frequency band can be formed in a monolithic IC without increasing the formation area of the signal detection circuit 60 with the capacitor 63 having a small capacitance value. (4) Since the capacitor 63 has a small capacitance value,
The charging current to the pMOS 62 can be reduced, and the pMOS 62 can be downsized.

FIG. 7 is a circuit diagram of a signal detection circuit showing a second embodiment of the present invention. This signal detection circuit 80
The difference from this embodiment is that the input
That is, an n-channel MOS transistor (hereinafter referred to as nMOS) 85 which is a transistor of a conductivity type opposite to that of a transistor is used. The drain D of the nMOS 85 is N
The PN transistor 84 is connected to the emitter, the source S is connected to the negative power supply potential Vb, and the gate G is connected to the input signal Si. PM which is an input transistor
OS 82, a capacitor 83, components of the inverter 86 is及beauty output means is the same as the first embodiment. The second embodiment has substantially the same advantages as those of the first embodiment, and furthermore, nM during the period when the input signal Si is "H".
The OS 85 is turned on, and has a function equivalent to that of the resistance element. While the input signal Si is “L”, the capacitor 83
At this time, the nMOS 85 is turned off, and the base B of the transistor 84 to the emitter E
No current flows. Therefore , the charging of the capacitor 83 is more effectively performed from the pMOS 82.

The present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, there are the following modifications. (I) Although the pMOSs 62 and 82 are used as the input transistors, they may be constituted by PNP transistors. In this case, a resistor is connected in series to the base electrode. (II) Although the capacitance elements are used as the capacitors 63 and 83, the invention is not limited to this. For example, the gate capacitance of a MOS transistor may be used. (III) was used inverters 66, 86 as output means is not limited to this, for example, 2 inputs to ground one input of NOR gate may function as an inverter, a 2-input NAND gate Etc. may be used. Further, a voltage comparator may be used. (IV) The NPN transistors 64 and 84 are used as the bipolar transistors.
An NP transistor may be used. (V) In the second embodiment, the nMOS 85 is used as the load MOS instead of the resistor 65, but a pMOS may be used by changing the polarity of the power supply potential.

[0016]

As described in detail above, according to the first and second aspects of the present invention, when the input transistor is off,
Discharge current of the definitive capacitor, bipolar transient scan
Through the base-emitter and discharge resistor means data, to be discharged becomes suppressed to a current corresponding to the current amplification factor of the bipolar transistor on the control node, the semiconductor integrated circuit input signal choice at a low frequency band Can be detected accurately.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a signal detection circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional signal detection circuit.

FIG. 3 is a voltage waveform diagram of a conventional signal detection circuit.

FIG. 4 is a partially enlarged waveform diagram of FIG. 3;

FIG. 5 is a circuit diagram of a main part of FIG. 1;

FIG. 6 is a voltage waveform diagram of the signal detection circuit according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram of a signal detection circuit according to a second embodiment of the present invention.

[Explanation of symbols]

62, 82 Input transistor (PMOS) 63, 83 Capacitor 65 Discharge resistance means (resistance) 66, 86 Signal output means (inverter) 64, 84 Bipolar transistor (NPN transistor) 85 Discharge resistance means (nMOS) Si input Signal Va , Vb power supply potential N Control node ib First current (base current) So Output signal i Second current

Claims (2)

(57) [Claims] 1. A first node to which a first power supply potential is applied.
Connected between the control node and the
An input transistor whose conduction state is controlled, A difference between the control node and the first power supply potential;
Connected to a second node supplied with a second power supply potential
When the input transistor is conductive, the control
A capacitor charged by current flowing through the node; A base is connected to the control node, and a collector is connected to the
A bipolar transistor connected to one node; The emitter of the bipolar transistor and the second node
Connected to the bipolar transistor and through the bipolar transistor.
To discharge the electric charge stored in the capacitor
Resistance means; Connected to the control node, depending on the potential of the control node
And output means for outputting the output signal.
Signal detection circuit. 2. The discharge resistance means, wherein a first electrode is provided in front of the discharge resistance means.
The second transistor is connected to the emitter of the bipolar transistor.
Is connected to the second node, and the control electrode is
An input signal is supplied, and the input transistor and the input transistor have opposite conductivity.
2. The transistor according to claim 1, wherein the transistor is a transistor.
Signal detection circuit.