KR960030398A - Esd 보호 회로를 갖는 반도체장치 - Google Patents

Esd 보호 회로를 갖는 반도체장치 Download PDF

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Publication number
KR960030398A
KR960030398A KR1019960001619A KR19960001619A KR960030398A KR 960030398 A KR960030398 A KR 960030398A KR 1019960001619 A KR1019960001619 A KR 1019960001619A KR 19960001619 A KR19960001619 A KR 19960001619A KR 960030398 A KR960030398 A KR 960030398A
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South Korea
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semiconductor device
protection
conduction resistance
terminals
terminal
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KR1019960001619A
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English (en)
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KR100194005B1 (ko
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가오루 나리따
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가네꼬 히사시
닛뽕덴끼 가부시끼가이샤
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Publication of KR960030398A publication Critical patent/KR960030398A/ko
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Publication of KR100194005B1 publication Critical patent/KR100194005B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

반도체장치는 공통 방전선, 입출력 단자의 한개와 방전선 사이에 연결된 제1보호장치와 Vcc와 접지선의 하나와 방전선 사이에 연결된 제2보호장치를 포함하는 반도체 회로를 갖는다. 제2반도체 장치는 제1반도체 장치의 도통 저항의 1/2 정도의 도통 저항을 갖는다. 각 전력 단자와 접지 단자는 큰 용량을 가지므로 CDM 테스트 동안에 전체적인 반도체장치의 충전후에 다량의 전하가 저장된다. 낮은 도통 저항은 반도체장치의 내부 회로와 입출력 버퍼가 CDM 테스트에서 반도체장치의 연속적인 접지 동안에 더 높은 퍼텐셜이 가해지는 것을 방지한다.

Description

ESD 보호 회로를 갖는 반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 본 발명의 실시예에 따른 반도체장치의 회로도, 제7a도는 제5도에서의 보호장치의 첫번째 일예의 회로도이고 제7b도는 제7a도의 보호장치의 단면도, 제8a도는 제5도에서의 보호장치의 두번째 일예의 회로도이고 제8b도는 제8a도의 보호장치의 단면도.

Claims (8)

  1. 기판과, 상기 기판 위에 형성되는 내부 회로와, 상기 내부 회로에 배치되며 복수의 제1단자와 복수의 제2단자를 포함하는 외부 단자군 및 공통 방전선, 상기 각 제1단자와 상기 공통 방전선 사이에 연결된 제1보호장치와 상기 각제2단자와 공통 방전선 사이에 연결된 제2보호장치를 포함하는 보호 회로를 구비하며, 상기 각 제1단자는 제1부유 용량을가지며, 상기 각 제2단자는 제1부유 용량 보다 더 큰 제 2부유 용량을 가지며, 상기 제1보호장치는 제1도통 저항을 가지며, 상기 제2보호장치는 상기 제1도통 저항보다 작은 제2도통 저항을 갖는 반도체장치.
  2. 제1항에 있어서, 상기 제1단자가 복수의 입출력 단자를 포함하며, 상기 제2단자가 적어도 한개의 전력 단자와 접지 단자를 포함하는 것을 특징으로 하는 반도체 장치.
  3. 제1항에 있어서, 상기 제2보호장치가 폭에 있어서 각각이 상기 제1보호장치의 전류 경로와 거의 동일한 전류 경로를 각각 갖는 복수의 보호 소자를 갖는 것을 특징으로 하는 반도체 장치.
  4. 제1항에 있어서, 상기 각 제1 및 제2보호장치가 클램프 소자를 포함하는 것을 특징으로 하는 반도체 장치.
  5. 제4항에 있어서, 상기 클램프 소자가 바이폴라 트랜지스터로 이루어지는 것을 특징으로 하는 반도체 장치.
  6. 제4항에 있어서, 상기 클램프 소자가 사이리스터로 이루어지는 것을 특징으로 하는 반도체 장치.
  7. 제4항에 있어서, 상기 클램프 소자가 NMOS FET로 이루어지는 것을 특징으로 하는 반도체 장치.
  8. 제4항에 있어서, 상기 각 제1와 제2보호장치가 상기 클램프 소자에 병렬로 연결된 다이오드를 또한 포함하는 것을 특징으로 하는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960001619A 1995-01-25 1996-01-25 Esd 보호 회로를 갖는 반도체장치 KR100194005B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7009375A JP2636773B2 (ja) 1995-01-25 1995-01-25 半導体集積回路装置
JP95-009375 1995-01-25

Publications (2)

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KR960030398A true KR960030398A (ko) 1996-08-17
KR100194005B1 KR100194005B1 (ko) 1999-06-15

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US (1) US5706156A (ko)
JP (1) JP2636773B2 (ko)
KR (1) KR100194005B1 (ko)
TW (1) TW366583B (ko)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5721658A (en) * 1996-04-01 1998-02-24 Micron Technology, Inc. Input/output electrostatic discharge protection for devices with multiple individual power groups
WO1997043407A1 (en) * 1996-05-10 1997-11-20 Phylomed Corporation Methods for oxidizing disulfide bonds using ozone
JP3144308B2 (ja) * 1996-08-01 2001-03-12 日本電気株式会社 半導体装置
KR100470994B1 (ko) * 1997-10-06 2005-07-07 삼성전자주식회사 반도체장치의정전기보호장치
US5991135A (en) * 1998-05-11 1999-11-23 Vlsi Technology, Inc. System including ESD protection
US6157530A (en) * 1999-01-04 2000-12-05 International Business Machines Corporation Method and apparatus for providing ESD protection
US6512662B1 (en) 1999-11-30 2003-01-28 Illinois Institute Of Technology Single structure all-direction ESD protection for integrated circuits
US6785109B1 (en) * 2000-01-10 2004-08-31 Altera Corporation Technique for protecting integrated circuit devices against electrostatic discharge damage
KR100337923B1 (ko) * 2000-07-24 2002-05-24 박종섭 Ｅｓｄ 보호 장치
US6784496B1 (en) 2000-09-25 2004-08-31 Texas Instruments Incorporated Circuit and method for an integrated charged device model clamp
US6635931B1 (en) 2002-04-02 2003-10-21 Illinois Institute Of Technology Bonding pad-oriented all-mode ESD protection structure
US6756834B1 (en) 2003-04-29 2004-06-29 Pericom Semiconductor Corp. Direct power-to-ground ESD protection with an electrostatic common-discharge line
JP6790705B2 (ja) * 2016-10-13 2020-11-25 セイコーエプソン株式会社 回路装置、発振器、電子機器及び移動体

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH065705B2 (ja) * 1989-08-11 1994-01-19 株式会社東芝 半導体集積回路装置
JP2972494B2 (ja) * 1993-06-30 1999-11-08 日本電気株式会社 半導体装置
US5521783A (en) * 1993-09-17 1996-05-28 Analog Devices, Inc. Electrostatic discharge protection circuit

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Publication number Publication date
JPH08204131A (ja) 1996-08-09
US5706156A (en) 1998-01-06
TW366583B (en) 1999-08-11
JP2636773B2 (ja) 1997-07-30
KR100194005B1 (ko) 1999-06-15

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