KR960026577A - 반도체 소자의 필드산화막 형성방법 - Google Patents

반도체 소자의 필드산화막 형성방법 Download PDF

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Publication number
KR960026577A
KR960026577A KR1019940038573A KR19940038573A KR960026577A KR 960026577 A KR960026577 A KR 960026577A KR 1019940038573 A KR1019940038573 A KR 1019940038573A KR 19940038573 A KR19940038573 A KR 19940038573A KR 960026577 A KR960026577 A KR 960026577A
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South Korea
Prior art keywords
oxide film
forming
semiconductor device
field oxide
silicon substrate
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KR1019940038573A
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English (en)
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KR0139267B1 (ko
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박미라
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김주용
현대전자산업 주식회사
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Priority to KR1019940038573A priority Critical patent/KR0139267B1/ko
Publication of KR960026577A publication Critical patent/KR960026577A/ko
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Publication of KR0139267B1 publication Critical patent/KR0139267B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체 소자의 필드산화막 형성방법에 관한 것으로, 질화막 상부에 층덮힘(Step coverage)특성이 좋지 않은 저온산화막(LTO막)을 형성한 후 블랜켓식각(Blanket etch)하여 실리콘기판을 리세스(recess)구조가 되도록 하므로써 실리콘기판으로 가해지는 스트레스(Stress)를 감소시켜 실리콘기판에 생성되는 결함(Defect)을 감소시키며 버즈빅(Bird's beak)을 감소시키는 동시에 평탄화특성을 향상시킬 수 있도록 한 반도체 소자의 필드산화막 형성방법에 관한 것이다.

Description

반도체 소자의 필드산화막 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2A 내지 제 2G 도는 본 발명에 따른 반도체 소자의 필드산화막 형성방법을 설명하기 위한 소자의 단면도.

Claims (3)

  1. 반도체 소자의 필드산화막 형성방법에 있어서, 실리콘기판상에 패드산화막, 버퍼폴리실리콘층 및 제 1 질화막을 순차적으로 형성시킨 후 소자분리마스크를 이용하여 필드영역의 제 1 질화막 및 버퍼폴리실리콘층을 순차적으로 식각하는 단계와, 상기 단계로부터 전체면에 제 2 질화막을 얇게 형성하고 그 상부에 저온산화막을 형성시키는 단계와, 상기 단계로부터 블랜켓식각을 실시하여 실리콘기판을 리세스구조로 식각한 후 잔류된 저온산화막을 제거하는 단계와, 상기 단계로부터 산화공정을 실시하여 필드영역에 필드산화막을 형성시키는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 필드산화막 형성방법.
  2. 제 1 항에 있어서, 상기 제 2 질화막의 두께는 100 내지 500Å인 것을 특징으로 하는 반도체 소자의 필드산화막 형성방법.
  3. 제 1 항에 있어서, 상기 블랜켓식각시 상기 저온산화막에 의해 상기 제 2 질화막의 손실이 방지되는 것을 특징으로 하는 반도체 소자의 필드산화막 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940038573A 1994-12-29 1994-12-29 반도체 소자의 필드산화막 형성방법 KR0139267B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940038573A KR0139267B1 (ko) 1994-12-29 1994-12-29 반도체 소자의 필드산화막 형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940038573A KR0139267B1 (ko) 1994-12-29 1994-12-29 반도체 소자의 필드산화막 형성방법

Publications (2)

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KR960026577A true KR960026577A (ko) 1996-07-22
KR0139267B1 KR0139267B1 (ko) 1998-06-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100439107B1 (ko) * 1997-12-29 2004-07-16 주식회사 하이닉스반도체 반도체소자의 소자분리막 형성방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100439107B1 (ko) * 1997-12-29 2004-07-16 주식회사 하이닉스반도체 반도체소자의 소자분리막 형성방법

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KR0139267B1 (ko) 1998-06-01

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