KR960026378A - 반도체의 제막방법 및 그 장치 - Google Patents
반도체의 제막방법 및 그 장치 Download PDFInfo
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- KR960026378A KR960026378A KR1019950047289A KR19950047289A KR960026378A KR 960026378 A KR960026378 A KR 960026378A KR 1019950047289 A KR1019950047289 A KR 1019950047289A KR 19950047289 A KR19950047289 A KR 19950047289A KR 960026378 A KR960026378 A KR 960026378A
- Authority
- KR
- South Korea
- Prior art keywords
- flow rate
- gas
- inert gas
- reaction gas
- atmospheric pressure
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract 13
- 239000004065 semiconductor Substances 0.000 title claims abstract 10
- 239000012495 reaction gas Substances 0.000 claims abstract 16
- 239000011261 inert gas Substances 0.000 claims abstract 14
- 239000010408 film Substances 0.000 claims abstract 7
- 239000007789 gas Substances 0.000 claims abstract 5
- 230000015572 biosynthetic process Effects 0.000 claims abstract 2
- 239000010409 thin film Substances 0.000 claims abstract 2
- 238000004519 manufacturing process Methods 0.000 claims 3
- 238000005259 measurement Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31608—Deposition of SiO2
- H01L21/31612—Deposition of SiO2 on a silicon body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
반응실에 반응개스, 불활성 개스를 동시에 공급하고, 양자의 유량을 조정함으로서 반응성 개스의 분압을 일정하게 하고 성막의 품질을 안정화시키는 대기압으로 웨이퍼에 얇은 막을 성막하는 반도체의 제막방법과 장치를 얻음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예를 나타내는 개략도.
Claims (9)
- 대기압에서 웨이퍼에 얇은 막을 성막하는 반도체의 제막방법에 있어서, 반응실에 반응성 개스, 불활성 개스를 동시에 공급하고, 반응성 개스의 분압을 일정하게 함을 특징으로 하는 반도체의 제막방법.
- 제1항에 있어서, 대기압의 변화에 대하여 불활성 개스의 유량을 변화시키고, 반응성 개스의 분압을 일정하게 함을 특징으로 하는 반도체의 제막방법.
- 제1항에 있어서, 대기압의 변화에 대하여 반응개스의 유량을 변화시키고, 반응성 개스의 분압을 일정하게 함을 특징으로 하는 반도체의 제막방법.
- 제1항에 있어서, 대기압의 변화에 대하여 반응개스, 불활성 개스 중 어느 한쪽의 유량을 규칙적으로 변화시키고 다른 쪽의 유량을 상기 한쪽의 유량변화, 대기압 변화에 대응시켜 변화시키고, 반응개스의 분압을 일정하게 함을 특징으로 하는 반도체의 제막형성.
- 제2항 내지 제4항 중 어느 한 항에 있어서, 웨이퍼의 제막처리전에 측정한 대기압을 기준으로 하여 반응개스의 유량, 불활성 개스의 유량을 결정하고, 제막처리 중 반응개스의 유량, 불활성 개스의 유량을 일정하게 함을 특징으로 하는 반도체의 제조방법.
- 제2항 내지 제4항 중 어느 한 항에 있어서, 웨이퍼의 제막처리 전 및 웨이퍼 처리 중에 적어도 1회 대기압을 측정하고, 측정한 각 대기압에 대응하여 반응개스의 유량, 불활성 개스의 유량을 결정하여 제막처리 중의 반응개스 유량, 불활성 개스 유량을 일정하게 함을 특징으로 하는 반도체의 제조방법.
- 제2항 내지 제4항 중 어느 한 항에 있어서, 대기압을 연속적으로 측정하고, 이 측정결과에 대응하여 반응개스의 유량, 불활성 개스의 중량 중 적어도 어느 한쪽을 연속적으로 변화시킴을 특징으로 하는 반도체의 제조방법.
- 반응관에 반응개스를 공급하는 반응개스 공급관과, 반응관에 불활성 개스를 공급하는 불활성 개스 공급관과 상기 반응개스 공급관, 불활성 개스 공급관에 각각 부착설치된 유량조정기와, 대기압을 측정하는 기압계와, 기압계의 측정결과에 따라 상기 양 유량조정기의 적어도 어느 한쪽의 유량제어를 하도록 하는 제어기로 설치구성됨을 특징으로 하는 반도체의 제막장치.
- 제8항에 있어서, 제어기가 대기압의 변화, 불활성 개스의 유량, 반응개스의 유량, 반응개스의 분압, 대가압을 변수로 하고, 반응개스 분압을 일정하게 하기 위한 반응개스, 불활성 개스의 유량을 연산하는 연산식을 가짐을 특징으로 하는 반도체의 제막장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6-334400 | 1994-12-19 | ||
JP6334400A JPH08172084A (ja) | 1994-12-19 | 1994-12-19 | 半導体成膜方法及びその装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960026378A true KR960026378A (ko) | 1996-07-22 |
KR100251134B1 KR100251134B1 (ko) | 2000-04-15 |
Family
ID=18276950
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950047289A KR100251134B1 (ko) | 1994-12-19 | 1995-12-07 | 반도체의 성막방법 및 그 장치 |
Country Status (4)
Country | Link |
---|---|
US (2) | US5798141A (ko) |
JP (1) | JPH08172084A (ko) |
KR (1) | KR100251134B1 (ko) |
TW (1) | TW279248B (ko) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2705592B2 (ja) * | 1994-10-14 | 1998-01-28 | 日本電気株式会社 | 半導体装置の製造方法 |
EP1271636A1 (en) * | 2001-06-22 | 2003-01-02 | Infineon Technologies AG | Thermal oxidation process control by controlling oxidation agent partial pressure |
JP4718054B2 (ja) * | 2001-07-30 | 2011-07-06 | 東京エレクトロン株式会社 | 縦型熱処理装置 |
JP4068327B2 (ja) * | 2001-10-11 | 2008-03-26 | 株式会社東芝 | 半導体製造装置と半導体装置の製造方法 |
JP2004259757A (ja) * | 2003-02-24 | 2004-09-16 | Seiko Epson Corp | 成膜時間の最適化方法及び成膜時間の最適化システム |
JPWO2006106859A1 (ja) * | 2005-03-31 | 2008-09-11 | 株式会社日立国際電気 | 半導体装置の製造方法、基板の製造方法および基板処理装置 |
JP5157100B2 (ja) * | 2006-08-04 | 2013-03-06 | 東京エレクトロン株式会社 | 成膜装置及び成膜方法 |
JP2008186865A (ja) * | 2007-01-26 | 2008-08-14 | Tokyo Electron Ltd | 基板処理装置 |
JP5457021B2 (ja) * | 2008-12-22 | 2014-04-02 | 東京エレクトロン株式会社 | 混合ガスの供給方法及び混合ガスの供給装置 |
JP6647260B2 (ja) * | 2017-09-25 | 2020-02-14 | 株式会社Kokusai Electric | 半導体装置の製造方法、基板処理装置及びプログラム |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3653399A (en) * | 1970-06-15 | 1972-04-04 | Nat Instr Lab Inc | Gas flow controlling system |
US5250323A (en) * | 1989-10-30 | 1993-10-05 | Kabushiki Kaisha Toshiba | Chemical vapor growth apparatus having an exhaust device including trap |
JPH0529443A (ja) * | 1991-07-25 | 1993-02-05 | Fujitsu Ltd | ウエーハ冷却装置及び冷却方法 |
JPH0532500A (ja) * | 1991-07-31 | 1993-02-09 | Hitachi Ltd | 大気圧による酸化・拡散処理条件の制御方法 |
JP3202401B2 (ja) * | 1993-03-26 | 2001-08-27 | 株式会社リコー | Mos型半導体装置におけるゲート酸化膜の製造方法 |
US5653807A (en) * | 1996-03-28 | 1997-08-05 | The United States Of America As Represented By The Secretary Of The Air Force | Low temperature vapor phase epitaxial system for depositing thin layers of silicon-germanium alloy |
-
1994
- 1994-12-19 JP JP6334400A patent/JPH08172084A/ja active Pending
-
1995
- 1995-11-30 TW TW084112764A patent/TW279248B/zh not_active IP Right Cessation
- 1995-12-07 KR KR1019950047289A patent/KR100251134B1/ko not_active IP Right Cessation
- 1995-12-13 US US08/571,538 patent/US5798141A/en not_active Expired - Lifetime
-
1998
- 1998-05-18 US US09/080,654 patent/US6051072A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6051072A (en) | 2000-04-18 |
US5798141A (en) | 1998-08-25 |
JPH08172084A (ja) | 1996-07-02 |
KR100251134B1 (ko) | 2000-04-15 |
TW279248B (ko) | 1996-06-21 |
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