KR960024939A - Data error detection device of synchronous multiplexer - Google Patents

Data error detection device of synchronous multiplexer Download PDF

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Publication number
KR960024939A
KR960024939A KR1019940033968A KR19940033968A KR960024939A KR 960024939 A KR960024939 A KR 960024939A KR 1019940033968 A KR1019940033968 A KR 1019940033968A KR 19940033968 A KR19940033968 A KR 19940033968A KR 960024939 A KR960024939 A KR 960024939A
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South Korea
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data
output
time signal
enable time
signal
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KR1019940033968A
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Korean (ko)
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KR100214049B1 (en
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이재환
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정장호
Lg 정보통신 주식회사
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Publication of KR960024939A publication Critical patent/KR960024939A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

본 발명은 동기식 다중화장치의 데이타 에러검출장치에 관한 것으로서, 동기식 페이로드 인에이블 타임(SPET) 신호와 J1타입(J1T) 신호를 입력신호로 받아 래치출력 인에이블 타임신호(EN)를 발생하는 래치출력 인에이블 타임 발생부와, 래치 출력 인에이블 타임 발생부에서 출력된 인에이블 타임신호(EN)로 인에이블되어 입력되는 데이타와 동기식 페이로드 인에이블 타임신호와 상기 J1 타임신호의 논리연산으로 데이타를 계산하는 데이타 계산부와, 데이타 계산부에서 출력된 데이타를 래치한 후 출력하는 데이타 래치 및 출력부와, 송신부에서 계산되어 경로 오버헤드(POH)내에 B3 위치에 입력된 제1데이타(B3 데이타)와 제1데이타를 이용하여 수신부의 데이타 계산부에서 출력된 제2데이타(B3' 데이타)를 비교하여 에러상태를 검출하는 비교판단부로 구성된 데이타 에러검출장치를 제공함으로써 데이타 전송경로의 에러를 모니터링할 수가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data error detection device of a synchronous multiplexing device. The present invention relates to a latch for generating a latch output enable time signal (EN) by receiving a synchronous payload enable time (SPET) signal and a J1 type (J1T) signal as input signals. Data that is enabled by the output enable time generation section, the enable time signal EN output from the latch output enable time generation section, and the data is inputted by the logical operation of the synchronous payload enable time signal and the J1 time signal. A data calculation unit for calculating the data, a data latch and output unit for latching the data output from the data calculation unit, and outputting the first data (B3 data) calculated at the transmitter and input to the B3 position within the path overhead (POH). ) And the first data to compare the second data (B3 'data) output from the data calculation section of the receiver to detect an error state By providing a data error detection device, an error in the data transmission path can be monitored.

Description

동기식 다중화장치의 데이타 에러검출장치Data error detection device of synchronous multiplexer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명에 의한 동기식 다중화장치의 데이타 에러검출장치 블록 구성도, 제6도는 제5도의 래치 출력 인에이블 타임 발생부의 인에이블 타이밍도로서, (가)는 SPET 타이밍도, (나)는 JIT 타이밍도, (다)는 인에이블 타이밍도.5 is a block diagram of a data error detector of the synchronous multiplexing apparatus according to the present invention, and FIG. 6 is an enable timing diagram of the latch output enable time generation unit of FIG. 5, (a) SPET timing diagram, and (b) The JIT timing diagram and (c) the enable timing diagram.

Claims (2)

동기식 페이로드 인에이블 타임(SPET)신호와 J1타입(J1T)신호를 입력신호로 받아 래치 출력 인이에블 타임신호(EN)를 발생하는 래치출력 인에이블 타입 발생부(10)와, 상기 래치 출력 인에이블 타임 발생부(10)에서 출력된 인에이블 타임신호(EN)로 인에이블되어 입력되는 데이타와 상기 동기식 페이로드 인에이블 타임신호와 상기 J1타임신호의 논리 연산으로 데이타를 계산하는 데이타 계산부(20)와, 상기 데이타 계산부(20)에서 출력된 데이타를 래치한 후 출력하는 데이타 래치 및 출력부(30)와, 송신부에서 계산되어 경로 오버헤드(PH)내에 소정(B3) 위치에 입력된 제1데이타(B3 데이타)와 상기 제1데이타를 이용하여 수신부의 상기 데이타계산부(20)에서 출력된 제3데이타(B3' 데이타)를 비교하여 에러상태를 검출하는 비교판단부(40)로 구성된 것을 특징으로 하는 동기식 다중화장치의 데이타 에러검출장치.A latch output enable type generator (10) for receiving a synchronous payload enable time (SPET) signal and a J1 type (J1T) signal as an input signal and generating a latch output enable time signal (EN); A data calculation unit that calculates data by performing a logical operation between the data input enabled by the enable time signal EN output from the enable time generator 10 and the synchronous payload enable time signal and the J1 time signal. (20), a data latch and output unit (30) for latching and outputting data output from the data calculation unit (20), and calculated by the transmitter and input at a predetermined (B3) position within the path overhead (PH) A comparison determination unit 40 for detecting an error state by comparing the first data (B3 data) and the third data (B3 'data) output from the data calculation unit 20 of the reception unit using the first data (B3 data). Characterized in that Data error detecting device according to the multiplexing-fed apparatus. 제1항에 있어서, 상기 데이타 계산부(20)는 상기 J1 타임신호와 상기 제1데이타를 배타적 논리합하여 출력하는 배타적 논리합 게이트(21)와, 상기 제1데이타를 상기 동기식 페이로드 인에이블 타임신호에 따라 논리곱하여 출력하는 제1앤드게이트(22)와, 상기 배타적 논리합 게이트(21)를 통해 출력된 상기 제1데이타를 상기 동기식 페이로드 인에이블 타임신호에 따라 논리곱하여 출력하는 제2앤드게이트(23)와, 상기 동기식 페이로드 인에이블 타임신호와 상기 J1 타임신호에 따라 상기 제1및 제2앤드게이트(22, 23)에서 출력되는 상기 제1데이타 값을 계산하는 제1플립플롭(24)과, 상기 제1플립플롭(25)에서 계산되어 출력된 데이타 값을 래치하여 출력하는 제2플립플롭(25)으로 구성된 것을 특징으로 하는 동기식 다중화장치의 데이타 에러검출장치.2. The data processing unit (20) of claim 1, wherein the data calculator (20) includes an exclusive OR gate (21) for outputting the exclusive OR of the J1 time signal and the first data, and the synchronous payload enable time signal. And a second AND gate outputting the result of performing a AND operation on the synchronous payload enable time signal based on the synchronous payload enable time signal. 23) and a first flip-flop 24 for calculating the first data value output from the first and second and gates 22 and 23 according to the synchronous payload enable time signal and the J1 time signal. And a second flip-flop (25) for latching and outputting the data value calculated and output from the first flip-flop (25). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940033968A 1994-12-13 1994-12-13 Data error detecting apparatus of synchronous multi-processing apparatus KR100214049B1 (en)

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Application Number Priority Date Filing Date Title
KR1019940033968A KR100214049B1 (en) 1994-12-13 1994-12-13 Data error detecting apparatus of synchronous multi-processing apparatus

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Application Number Priority Date Filing Date Title
KR1019940033968A KR100214049B1 (en) 1994-12-13 1994-12-13 Data error detecting apparatus of synchronous multi-processing apparatus

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KR960024939A true KR960024939A (en) 1996-07-20
KR100214049B1 KR100214049B1 (en) 1999-08-02

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