KR960027628A - Transient Bit Error Detection Circuit of Digital Transmission Threshold Signal - Google Patents

Transient Bit Error Detection Circuit of Digital Transmission Threshold Signal Download PDF

Info

Publication number
KR960027628A
KR960027628A KR1019940038659A KR19940038659A KR960027628A KR 960027628 A KR960027628 A KR 960027628A KR 1019940038659 A KR1019940038659 A KR 1019940038659A KR 19940038659 A KR19940038659 A KR 19940038659A KR 960027628 A KR960027628 A KR 960027628A
Authority
KR
South Korea
Prior art keywords
signal
bit error
detection circuit
digital transmission
counting
Prior art date
Application number
KR1019940038659A
Other languages
Korean (ko)
Other versions
KR0135334B1 (en
Inventor
하정민
Original Assignee
박성규
대우통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박성규, 대우통신 주식회사 filed Critical 박성규
Priority to KR1019940038659A priority Critical patent/KR0135334B1/en
Publication of KR960027628A publication Critical patent/KR960027628A/en
Application granted granted Critical
Publication of KR0135334B1 publication Critical patent/KR0135334B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/203—Details of error rate determination, e.g. BER, FER or WER

Landscapes

  • Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

본 발명은 디지탈 전송계위신호의 과도 비트에러 검출회로에 관한 것으로서 디지탈 전송계위신호의 과도 비트에러 검출회로는 클럭신호를 수신하여 미리 설정된 타임 인터발을 가지는 리셋 신호들을 발생하기 위한 리셋수단과 ; 상기 리셋 신호들간의 타임 인터발 동안에 인가되는 바이폴라 바이올레이션 신호의 갯수를 카운팅하여 카운팅 결과 신호를 출력하기위한 카운팅수단과 ; 상기 카운팅수단으로부터 출력되는 상기 카운팅 결과 신호를 상기 리셋신호들 중의 제 1 리셋 신호로써 감시하여 상기 바이폴라 바이올레이션 신호에 대한 과도 비트에러를 나타내는 과도 에러 선언 신호를 생성하는 판정수단을 포함한다.The present invention relates to a transient bit error detection circuit of a digital transmission threshold signal, the transient bit error detection circuit of a digital transmission threshold signal comprising: reset means for receiving a clock signal and generating reset signals having a predetermined time interval; Counting means for counting the number of bipolar vibration signals applied during the time interval between the reset signals and outputting a counting result signal; And determining means for monitoring the counting result signal output from the counting means as a first one of the reset signals to generate a transient error declaration signal indicative of a transient bit error for the bipolar vibration signal.

따라서, 디지탈 전송계위신호의 수신시 바이폴라 바이올레이션 신호를 검출한 후 누적하여 과도 비트에러의 정도를 체크함에 의해 수신되는 신호의 신뢰성을 향상시키므로 전송의 품질을 향상시킬 수 있어 장비의 판매 경쟁력을 높일 수 있다.Therefore, when receiving the digital transmission boundary signal, the bipolar vibration signal is detected and accumulated, and the reliability of the received signal is improved by checking the degree of transient bit error. Therefore, the quality of transmission can be improved, thereby enhancing the sales competitiveness of the equipment. Can be.

Description

디지탈 전송계위신호의 과도 비트에러 검출회로Transient Bit Error Detection Circuit of Digital Transmission Threshold Signal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 디지탈 전송계위신호의 과도 비트에러 검출회로 블럭도.3 is a block diagram of a transient bit error detection circuit of a digital transmission threshold signal according to the present invention.

Claims (4)

디지탈 전송계위신호의 과도 비트에러 검출회로에 있어서 ; 클럭신호를 수신하여 미리 설정된 타임 인터발을 가지는 리셋 신호들을 발생하기 위한 리셋수단과 ; 상기 리셋 신호들 간의 타임 인터발 동안에 인가되는 바이폴라 바이올레이션신호의 개수를 카운팅하여 카운팅 결과 신호를 출력하기 위한 카운팅수단과 ; 상기 카운팅수단으로부터 출력되는 상기 카운팅 결과 신호를 상기 리셋신호들 중의 제 1 리셋 신호로써 감시하여 상기 바이폴라 바이올레이션 신호에 대한 과도 비트에러를 나타내는 과도 에러 선언 신호를 생성하는 판정 수단을 포함하는 디지탈 전송계위신호의 과도 비트에러 검출회로.A transient bit error detection circuit of a digital transmission threshold signal; Reset means for receiving a clock signal and generating reset signals having a predetermined time interval; Counting means for counting the number of bipolar vibration signals applied during the time interval between the reset signals and outputting a counting result signal; A digital transmission level comprising determining means for monitoring the counting result signal output from the counting means as a first reset signal among the reset signals to generate a transient error declaration signal indicative of a transient bit error for the bipolar vibration signal. Transient bit error detection circuit of the signal. 제1항에 있어서, 상기 카운팅 수단이, 클럭단이 상기 바이폴라 바이올레이션신호를 수신하고 칩인에이블단으로 공급 전원을 수신하여 상기 신호를 카운팅하는 제1카운터와 ; 클럭단으로 상기 제1카운터 캐리단의 출력을수신하고 칩 인에이블단으로 상기 공급 전원을 수신하여 상기 카운팅 결과 신호를 출력하는 제2카운터와 ; 상기 제1 및 제2카운터의 로드단에 파워리셋 신호와 제2리셋신호를 오아 게이팅한 출력을 제공하는 오아 게이트로 구성된 디지탈 전송계위신호의 과도 비트에러 검출 회로.2. The apparatus of claim 1, wherein the counting means comprises: a first counter at which a clock stage receives the bipolar vibration signal and receives a supply power to a chip enable stage to count the signal; A second counter configured to receive an output of the first counter carry stage at a clock stage and receive the supply power at a chip enable stage to output the counting result signal; 10. A transient bit error detection circuit of a digital transmission threshold signal comprising an OR gate providing an output obtained by orating a power reset signal and a second reset signal to the load terminals of the first and second counters. 제1항에 있어서, 상기 판정 수단이, 상기 카운팅 결과 신호를 래치하여 상기 선언 신호를 제공하는 2개의 래치소자와, 상기 래치소자를 리세트하기 위한 오아 게이트로 구성된 디지탈 전송계위신호의 과도 비트에러 검출회로.2. The transient bit error of the digital transmission threshold signal according to claim 1, wherein said determining means comprises two latch elements for latching said counting result signal to provide said declaration signal, and an ore gate for resetting said latch element. Detection circuit. 제1항에 있어서, 상기 클럭은 라인 인터페이스부로부터 제공되는 시스템클럭인 디지탈 전송계위신호의 과도 비트에러 검출회로.2. The transient bit error detection circuit of claim 1, wherein the clock is a system clock provided from a line interface unit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038659A 1994-12-29 1994-12-29 Circuit for detecting data errors in digital transmitting hierarchical signal KR0135334B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940038659A KR0135334B1 (en) 1994-12-29 1994-12-29 Circuit for detecting data errors in digital transmitting hierarchical signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940038659A KR0135334B1 (en) 1994-12-29 1994-12-29 Circuit for detecting data errors in digital transmitting hierarchical signal

Publications (2)

Publication Number Publication Date
KR960027628A true KR960027628A (en) 1996-07-22
KR0135334B1 KR0135334B1 (en) 1998-04-27

Family

ID=19404881

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940038659A KR0135334B1 (en) 1994-12-29 1994-12-29 Circuit for detecting data errors in digital transmitting hierarchical signal

Country Status (1)

Country Link
KR (1) KR0135334B1 (en)

Also Published As

Publication number Publication date
KR0135334B1 (en) 1998-04-27

Similar Documents

Publication Publication Date Title
KR920005171A (en) Semiconductor memory with successively clocked call codes for entering test mode
KR900014984A (en) Circuit element and method for providing output signal representation of time delay between two asynchronous clock signals
KR980007258A (en) I²C communication device using general purpose microcomputer
GB2243257A (en) Pulse detection circuits
KR960027628A (en) Transient Bit Error Detection Circuit of Digital Transmission Threshold Signal
KR890001272A (en) Signal discrimination circuit
KR970055399A (en) Clock discrimination device
KR100243755B1 (en) Cluck pail detecting apparatus
KR200334102Y1 (en) Clock monitoring circuit using shift register
KR900002624A (en) Clamp Pulse Writing Circuit
KR100463846B1 (en) Clock Monitoring Apparatus of Switching System
SU1088143A2 (en) Device for detecting errors of bipolar signal
JP2531446B2 (en) Clock monitoring circuit
KR960003182A (en) Line Redundancy Unit in HDLC NRZI Communication System
KR940019073A (en) Floating detection circuit
KR900002618A (en) Facsimile Code Detection Circuit
SU1123051A1 (en) Device for recording digital information
KR960025098A (en) Fault location detection circuit between ASICs in multi-stage broadband switch
SU1552032A1 (en) Device for detecting leakage
KR100206906B1 (en) Timer/counter circuit
KR100207652B1 (en) Error detector of tsx in the optical transmitter
KR930013741A (en) Clock Error Detection and Selection Circuit
KR890014996A (en) Automatic meter reading
KR940020219A (en) Timing verification circuit
JPH05236026A (en) Digital signal monitor circuit

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20010331

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee