KR100214049B1 - Data error detecting apparatus of synchronous multi-processing apparatus - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data error detection device of a synchronous multiplexing device. The present invention relates to a latch for generating a latch output enable time signal (EN) by receiving a synchronous payload enable time (SPET) signal and a J1 time (J1T) signal as input signals. The data is enabled by the output enable time generation unit and the enable time signal EN output from the latch output enable time generation unit, and is input by the logical operation of the synchronous payload enable time signal and the J1 time signal. A data calculation unit for calculating the data, a data latch and output unit for latching and outputting the data output from the data calculation unit, and first data (B3 data) calculated at the transmitter and input at the position B3 within the path overhead POH. ) And a comparison determination unit for detecting an error state by comparing the second data (B3 'data) output from the data calculation unit of the receiver using the first data. By providing a data error detection unit it can be monitored for errors in the data transmission path.

Description

Data error detection device of synchronous multiplexer

1 is a block diagram of a general STS-1 frame format.

2 is a schematic diagram of a typical STS-1 SPE and POH.

3 is a block diagram of a general STS-N frame format.

4 is a conceptual diagram of general B3 data generation.

5 is a block diagram of a data error detection apparatus of a synchronous multiplexing apparatus according to the present invention.

FIG. 6 is an enable timing diagram of the latch output enable time generator of FIG.

6A is a SPET timing diagram.

6B is a J1T timing diagram.

6C is an enable timing diagram.

FIG. 7 is a block diagram of an internal data calculator in FIG.

* Explanation of symbols for main parts of the drawings

10: Latch output enable time generator

20: data calculation section 21: exclusive OR gate

22, 23: first and second end gates

24: 1st flip flop 25: 2nd flip flop

30: data latch and output unit 40: comparison determination unit

The present invention relates to a synchronous multiplex transmission apparatus, and more particularly, to a data error detection apparatus of a synchronous multiplexing apparatus for detecting an error of B3 data in a synchronous multiplexing apparatus.

In general, the STS-1 frame format is 9 rows and 90 bytes in size, as shown in FIG. 1, and consists of 3 bytes of transmission overhead and 87 bytes of STS-1 packaging capacity.

The SPE (Synchronous Payload Envelope) present in the STS-1 frame format of FIG. 1 exists between the entire frame formats transmitted and corresponds to user data during a telephone call.

Thus, as shown in FIG. 2, the SPE has an STS-1 path overhead (POH: eg J1, B3, C2, G1, etc.) with one byte at the beginning of each of the nine rows, and the remaining STS. -1 consists of 86 bytes of payload capacity.

In the above case, the B3 data exists in the path overhead, and in the case of the STS-N frame format, there are N B3 data as shown in FIG.

This B3 data monitors the errors in the path, and consists of bit interleaved parity (BIP) -8 codes and uses even parity.

Further, according to FIG. 4, the data flow configuration of the B3 data is composed of an X th frame, an X-1 th frame, and an X-2 th frame, and an SPE flows between the frames, and the X th frame is included in the SPE. The B3 data, the X-2nd B3 data, and the like exist respectively, and before each SPE, transmission overhead flows first.

As such, the B3 data existing in the SPE is calculated by the BIP-8 from the previous STS SPE and inputted into the current B3 position.

That is, the (X-1) th STS SPE is calculated by inputting the BIP-8 into the X th B3 position, but there is a problem that an error occurs when performing the path error monitoring function.

The present invention provides a data error detection apparatus of a synchronous multiplexer for more efficient data transmission by detecting an error of B3 data present in the path overhead in the SPE in a synchronous transmission apparatus. have.

The present invention for achieving the above object will be described in detail with reference to the accompanying drawings.

According to the configuration of the present invention, as shown in FIG. 5, a synchronous payload enable time (SPET) signal and a J1 time (J1T) signal (that is, a time for indicating the position of the SPE) are input signals. Receive latch enable enable time signal EN and generate an enable time signal EN output from the latch output enable time generation unit 10 to enable the latch output enable time signal EN. A data calculation unit 20 that calculates data by logical operation of the input data, the synchronous payload enable time signal SPET, and the J1 time signal, and latches the data output from the data calculation unit 20. The data latching unit outputs the data latching unit and the output unit 30 to be outputted afterwards, and the first data (B3 data) calculated at the transmitter unit and input to the B3 position in the path overhead POH and the first data unit. Outputted at 20 And a comparison determination unit 40 for comparing the second data (B3 data) and detecting an error state.

The data calculation unit 20 outputs an exclusive OR gate 21 for exclusively ORing the J1 time signal and the first data and outputs the AND data by logically multiplying the first data according to the synchronous payload enable time signal. A first end gate 22 and a second end gate 23 for performing a logical AND operation on the first data output through the exclusive OR gate 21 according to the synchronous payload enable time signal; And a first flip-flop 25 for calculating the first data value output from the first and second and gates 22 and 23 according to the synchronous payload enable time signal and the J1 time signal.

Referring to the operation of the present invention by the above configuration, the latch output enable time generation section 10 receives the SPET and J1T as input, the first data (that is, as shown in FIG. 6B) as shown in FIG. , B3 data).

Here, the SPET enters the input signal because the position of the J1T signal changes when the STUFF occurs as shown in Figs. 6B and 6C (enable timing diagram).

The latch output enable time generator 10 receiving the signals SPET and J1T outputs an enable signal.

The data calculation unit 20 receiving the enable signal, the first data (8 bits) and the signals SPET and J1T performs data calculation through a logic operation element, and the calculated data is the latch output in. The second data (ie, B3 'data) is output only to every J1T signal through the data latch and the output unit 30 enabled by the enable signal generated by the enable time generator 10.

Accordingly, the comparison determination unit 40 compares the value of the first data calculated by the transmitter and received at the receiver and detects and outputs an error state.

A detailed operation of the data calculator 20 will be described with reference to FIGS. 6 and 7 as follows.

The 8-bit first data calculated by the transmitter and received by the receiver has a high signal state when the J1T signal is high (see (a) of FIG. 6). A normal J1 value is input to the J input terminal of the input terminal, and a J1 value inverted by the exclusive OR gate 21 is input to the K input terminal and latched by the second flip-flop 25 formed of the D flip-flop. The data is loaded.

Here, when the SPET is in the high state (H) and J1T is in the low state (L), the outputs of the first and second and gates 22 and 23 are the same as the values of the data of the first flip-flop 24. It is input to the K input terminal to calculate the data.

However, if the SPET is in the low state L, that is, the TOH time as shown in (a) of FIG. 6, the previous value is the previous value since the outputs of the first and second end gates 22 and 23 are low. Keep it.

Accordingly, the result of the first flip-flop 24 is the same as the result outputted by the exclusive OR gate 21 on the SPE data.

As described above, the present invention performs the function of monitoring the error of the path by detecting the B3 data of the synchronous transmission device and comparing the B3 value of the received data to smoothly perform the basic function that the synchronous transmission device should have.

Claims (2)

A latch output enable time generator 10 which receives a synchronous payload enable time signal and a J1 time J1T signal as an input signal and generates a latch output enable time signal EN; A data calculation unit configured to calculate data by performing a logical operation between the data which is enabled by the enable time signal EN output from the enable time generator 10 and the synchronous payload enable time signal and the J1 time signal; 20), the data latch and output unit 30 for latching and outputting the data output from the data calculating unit 20, and the data calculated by the transmitting unit and input to a predetermined (B3) position within the path overhead (POH). By comparing the first data (B3 data) and the second data (B3 'data) output from the data calculating section 20 of the receiving unit using the first data to the comparison determination unit 40 for detecting an error state Characterized by Data error detecting apparatus of a synchronous multiplexing device. The method of claim 1, wherein the data calculator 20 includes an exclusive OR gate 21 for exclusively ORing the J1 time signal and the first data and outputting the first data to the synchronous payload enable time signal. And a second AND gate outputting the result of performing a AND operation on the synchronous payload enable time signal based on the synchronous payload enable time signal. 23) and a first flip-flop 24 for calculating the first data value output from the first and second and second gates 22 and 23 according to the synchronous payload enable time signal and the J1 time signal. And a second flip-flop (25) for latching and outputting the data value calculated and output by the first flip-flop (25).