KR930008681B1 - B.i.p. checking circuit of synchronous multi-device - Google Patents

Abstract

A BIP (bit interleaved paring) inspection circuit for monitoring multiplexing function state of TUG21 in a synchronous multiplexing apparatus includes a BIP value generator for calculating to supply BIP value with respect to corresponding VC12 multiframe by using parallel TUG21 data formed from the VC12 multiframe as an input by a V5 path overhead period, a BIP timing generator connected to the BIP value generator for producing to supply BIP clocks, system clocks, BIP reset clocks and BIP latch clocks which are required for generating the BIP value to the BIP value generator by using 864KHz clock, 280KHz clock and 2KHz clock as inputs, and a BIP comparing unit connected to the BIP value generator for comparing the BIP value calculated in the BIP value generator with the BIP value extracted from the TUG21 signal, thereby heightening efficiency of the circuit and stabilizing the low-speed circuit by lowering the timing speed according to the parallel data.

Description

BIP Inspection Circuit of Synchronous Multiple Devices

1 is a configuration diagram of a VC12 multiframe.

2 is a TUG21 signal waveform diagram.

3 is a block diagram of a BIP inspection circuit according to the present invention.

4 is a detailed configuration diagram of the BIP timing generator of FIG.

5 is a signal waveform diagram of each part of FIG.

6 is a detailed configuration diagram of the BIP value generator of FIG.

7 and 6 are detailed circuit diagrams of a BIP value generator.

8 is a detailed circuit diagram of the BIP comparison unit of FIG.

* Explanation of symbols for main parts of the drawings

10: BIP value generator 20: BIP comparison unit

30: BIP timing generator 40: BIP latch clock generator

50: BIP reset clock generator 60: the system clock generator

70, 71: BIP generating part 41 to 43, 51 to 53, 95, 96: D flip-flop

54 to 56 AND gates 61 to 63, 92, inverter

81 to 86: exclusive OR gate 91 to 94: NAND gate

The present invention relates to a bit interleaved parity (BIP) test circuit for TUG21 multi-function state monitoring of a synchronous multi-device using SDH (Synchronous Digital Hierarchy) internationally standardized by CCITT.

FIG. 1 is a configuration diagram of a VC12 multiframe, and FIG. 2 is a TUG21 signal waveform diagram.

In the synchronous multiplexer, as shown in FIG. 1, the asynchronous DS1 slave signal is mapped to a VC12 multiframe composed of 140 bytes in synchronization with a 2.240 MHz clock, and then serialized / parallel (2.240 Mbps / 8 = 280 Kbps) conversion.

864 kHz and 280 kHz clocks are supplied and formed using the parallel VC12 multiframe TU12 signal using a FIFO (First In First Out) scheme. The three TU12 signals are formed of TU21 signals as shown in FIG.

The path performance between the VC12 of the synchronous digital multiple device is monitored by parity calculation of the BIP bit, which is a performance monitoring bit of the V5 path overhead present in the VC12 multiframe. That is, the path performance monitoring between VC12 calculates the sender BIP, inserts it into the BIP-2 bit of the V5 path overhead, and transmits it. The receiver also calculates the BIP and compares the received BIP value with the received BIP value by a specified time. Cumulative analysis can monitor the performance of its intervals.

Accordingly, an object of the present invention is to provide a BIP detection circuit for detecting a hardware failure in a section in which a serial VC12 multiframe is processed in 8 bits in parallel and multiplexed with a TUG21 signal.

In order to achieve the above object, the present invention provides a BIP check circuit for TUG21 multi-function state monitoring of a synchronous multi-valued value, and inputs parallel TUG21 data formed from VC12 multiframes to each corresponding VC12 multiframe at V5 path overhead period. A BIP value generating means for calculating and generating a BIP value, the BIP value being connected to the BIP value generating means and inputting a 864 kHz clock, a 280 kHz clock, and a 2 ㎑ clock to the BIP value generating means to generate the BIP value. BIP timing generating means for generating and supplying a clock, a system clock, a BIP reset clock, and a BIP latch clock, and a BIP value connected to the BIP value generating means and a BIP value calculated by the BIP value generating means and a BIP extracted from the TUG21 signal. It consists of BIP comparison means for comparing values.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

3 is a block diagram showing a schematic configuration of a BIP inspection circuit according to the present invention, where 10 is a BIP value generator, 20 is a BIP comparator, and 30 is a BIP timing generator.

As shown in FIG. 3, the BIP inspection circuit according to the present invention uses a TUG21 signal formed from a VC12 multiframe as an input and calculates and generates a BIP value for each corresponding VC12 multiframe at a V5 path overhead period. 10, a timing generator 30 for supplying a clock necessary for generating a BIP value to the BIP value generator 10, and a BIP value generated by the BIP value generator 10 and the TUG21 frame. It consists of a BIP comparison unit 20 for extracting and comparing the BIP value inserted in the.

4 is a detailed configuration diagram of the BIP timing generator 30 of FIG. 3, and FIG. 5 is a signal waveform of each part of FIG. 4, 40 is a BIP latch clock generator, and 41 to 43, 51 to 53 are D flips. Flop, 50 denotes a BIP reset clock generator, 54 to 56 denotes an AND gate, 60 denotes a system clock generator, and 61 to 63 denote inverters.

A detailed configuration of the BIP timing generator 30 according to the present invention will be described with reference to FIGS. 4 and 5 as follows.

System clock generator 60 for generating system clocks (SYSCK-A, SYSCK-B, SYSCK-C) by inputting 280 비트 TUG21 bit frame data clocks (TUGBF-A, TUGBF-B, TUGBF-C) A BIP latch clock generator 40 generating a BIP latch clock (BIPLAT-A, BIPLAT-B, BIPLAT-C) for latching the BIP value by inputting the clock signal OTUV5B1 of 2 kHz; BIP latch clock (BIPLAT-A) of the BIP latch clock generator 40 and the 864 kHz clock which is the TUG21 clock, and the system clocks (SYSCK-A, SYSCK-B, SYSCK-C) and BIP of the system clock generator 60 BIP reset clocks BIPRES-A and BIPRES- for resetting the BIP value generator 11 by inputting the BIP latch clocks BIPLAT-A, BIPLAT-B, and BIPLAT-C of the latch clock generator 40. B, BIPRES-C) to generate a BIP reset clock generating section (50).

The 280 T TUG21 bit frame data (TUGBF-A, TUGBF-B, TUGBF-C) is a BIP clock (BIPCK-A, BIPCK-B, BIPCK-) that extracts the corresponding data to calculate the BIP value from the TUG21 signal. C), inputted to the system clock generator 60 composed of inverters 61, 62, and 63, and inverted through the inverters 61, 62, and 63, and the system clocks SYSCK-A, SYSCK-B, SYSCK -C).

The BIP latch clock generator 40 generates a BIP latch clock BIPLAT-A by using the clock signal OTUV5B1 of 2 ㎑ as a data input and the BIP clock BIP-B as a clock input. The flip-flop 41, the D-flip which generates the BIP latch clock BIPLAT-B by using the output Q1 of the D flip-flop 41 as a data input and the BIP clock BIPCK-C as a clock input. A flop 42 and a D flip-flop that generate a BIP latch clock BIPLAT-C by using the output Q2 of the D flip-flop 42 as a data input and the BIP clock BIPCKT-A as a clock input. It consists of 43.

The BIP reset clock generator 50 connects an AND gate 54 to which the system clock SYSCK-B and the BIP latch clock BIPLAT-A are input, and a data input terminal to an output terminal of the AND gate 54. D flip-flop 51 for generating a BIP reset clock BIPRES-A, AND gate 55 for inputting the system clock SYSCK-C and BIP latch clock BIPLAT-B, and the AND gate 53, the D input flop 52 is connected to the output terminal of the output terminal to generate the BIP reset clock BIPRES-B, and the AND is inputted to the system clock SYSCK-A and the BIP latch clock BIPLAT-C. And a D flip-flop 53 which is connected to a gate 56 and an output terminal of the AND gate 56 to generate a BIP reset clock BIPRES-C. The D flip-flops 51, 52, and 53 864 클럭 clock is input to the clock input terminal.

6 is a detailed configuration diagram of the BIP value generator 10 of FIG. 3, wherein 70 and 71 represent BIP generators and 81 to 86 represent exclusive OR gates, respectively.

The parallel-converted TUG21 data includes first and third bits D0 and D2, fifth and seventh bits D4 and D6, second and fourth bits D1 and D3, and sixth and eighth bits. (D5, D7) are divided into even and odd bits and input to the two input exclusive OR gates 81, 82, 83, and 84, respectively, and the outputs of the exclusive OR gates 81, 82, 83, and 84 are output to the TUG21 data. Are divided into even and odd bits, respectively, to be inputs of the two input exclusive OR gates 85 86, and the outputs of the exclusive OR gates 85 86 are input to the BIP generators 70 and 71, respectively, and the BIP generators 70, 71) BIP latch clocks (BIPLAT: BIPLAT-1, BIPLAT-B, LBIPLAT-C), BIP reset clocks (BIPRES: BIPRES-A, BIPRES-B, BIPRES-C), system clocks (SYSCK: SYSCK-A, BIP values are generated by inputting SYSCK-B, SYSCK-C), BIP clocks (BIPCK: BIPCK-A, BIPCK-B, BIPCK-C), and reset signals (RESETB).

7 is a detailed circuit diagram of the BIP generators 70 and 71 of FIG. 6, 91 and 94 represent NAND gates, 92 and 93 inverters, and 95 and 96 D flip flops, respectively.

As shown in FIG. 7, the BIP generation unit 70, 71 has a NAND gate 91 for inputting the output of the exclusive OR gates 85,86 and a BIP clock BIPCK, and the reset signal RESETB. ), An inverter 93 for inverting the BIP reset clock BIPRES, an AND gate 94 for inputting the outputs of the inverters 92, 93, and the AND gate 94 A clear terminal is connected to an output terminal, an enable terminal TE is connected to an output terminal of the NAND gate 91, the system clock SYSCK is a clock input, and the inverted output terminal Q7n is fed back to a data input terminal ( A D flip-flop 95 connected to D1) and a feedback output terminal Q7 connected to a state operation signal input terminal T1, and a data input terminal connected to an output terminal Q7 of the D flip-flop 95; D plug having the BIP latch clock (BIPLAT) as a clock input and a clear terminal (CD) connected to the output terminal of the inverter 92. It consists of a flop 96.

The BIP clock BIPCK outputs a "LOW" state signal, and a "high" state signal is inputted to the enable terminal TE of the D flip-flop 95. When the output Q7 becomes high, it is enabled and operated. However, when the output Q7 becomes high, the BIP value is extracted by the system clock SYSCK and output to the D flip-flop 96. Reference numeral 96 latches the BIP latch clock BIPLAT as a clock and outputs a BIP value to the BIP comparator 20.

The inverters 92 and 93 and the NAND gate 94 output signals for clearing the D flip-flops 95 and 96 from which the BIP value is extracted to clear terminals of the D flip-flops 96 and 96. Enter (CD).

8 is a detailed circuit diagram of the BIP comparator 20 of FIG. 3, where 100 and 101 represent an exclusive OR gate.

The BIP comparator 20 uses two bits of BIP values of the parallel TUG21 data as one input and two exclusive BIP values calculated from the BIP generator 10 as other inputs, respectively. BIP error that is composed of OR gates (100, 101) and compares the BIP value extracted from the TUG21 data with the BIP value calculated by the BIP value generator (10) through the exclusive OR gate (100, 101). It outputs and passes it to the place to monitor.

The present invention constructed and operated as described above uses a BIP-2 calculation circuit existing on a serial VC 12 multiframe for overhead BIP-2 and internal path monitoring, and uses 8 bit parallel TUG21 data for the same BIP-. By using two calculation circuits, circuit efficiency is achieved, and the timing required for BIP-2 calculation of TUG21 operates according to the parallel data, so that the speed is lowered, so that the circuit stability at low speed is achieved.

Claims (7)

In the bit interleaved paring (BIP) test circuit for TUG21 multi-function status monitoring of a synchronous multiple device; BIP value generation means 10 and BIP value generation means 10 for calculating and generating BIP values for the respective VC12 multiframes with V5 path overhead periods as inputs of parallel TUG21 data formed from VC12 multiframes. BIP clock (BIPCK-A, BIPCK-B, BIPCK-C) required for generating the BIP value to the BIP value generating means 10 by inputting the 864 ㎑ clock, 280 ㎑ clock and 2 ㎑ clock (OUTV5B1). , System clocks (SYSCK-A, SYSCK-B, SYSCK-C), BIP reset clocks (BIPRES-A, BIPRES-B, BIPRES-C) and BIP latch clocks (BIPLAT-A, BIPLAT-B, BIPLAT-C) Is connected to the BIP timing generating means 30 and the BIP value generating means 10 and compares the BIP value calculated by the BIP value generating means 10 with the BIP value extracted from the TUG21 signal. BIP inspection circuit, characterized in that consisting of the BIP comparison means 20. 2. The BIP value generating means (10) according to claim 1, wherein the BIP value generating means (10) comprises first and second exclusive logical sum means (81, 82) for inputting even bits of the parallel TUG21 data and odd bits of the parallel TUG21 data. The third and fourth exclusive OR means 83 and 84, the fifth exclusive OR means 85 connected to an output end of the first and second exclusive OR means 81 and 82, and the third and fourth A sixth exclusive OR means 86 connected to an output end of the exclusive OR means 83 and 84, and a BIP clock output from the output of the fifth exclusive OR means 85 and the timing generating means 30. -A, BIPCK-B, BIPCK-C), system clocks (SYSCK-A, SYSCK-B, SYSCK-C), BIP reset clocks (BIPRES-A, BIPRES-B, BIPRES-C), and BIP latch clocks ( Outputs of the first BIP generating means 70 and the sixth exclusive logical sum means 86 for inputting BIPLAT-A, BIPLAT-B, BIPLAT-C) and the reset signal RESETB; BIP test circuit according to claim 2 consisting of the BIP generation means 71 that the clock output from the timing generating means 30 as input. 2. The BIPCK (BIPCK-A, BIPCK-B, BIPCK-C) of 280 하는 according to claim 1, wherein the timing generating means 30 extracts the corresponding data to calculate the BIP value from the TUG21 data. A system clock generating means (60) configured to generate the system clocks (SYSCK-A, SYSCK-B, SYSCK-C), the first, second, and third inverters 61, 62, and 63 serving as inputs; BIP latch clock generation to generate the BIP latch clocks (BIPLAT-A, BIPLAT-B, BIPLAT-C) by inputting the BIP clocks (BIPCK-A, BIPCK-B, BIPCK-C) and 2 ㎑ clock (OTUV5B1) Means 40, and the BIP latch clock generating means 40 and the system clock generating means 60, the BIP latch clocks of the BIP latch clock generating means 40 (BIPLAT-A, BIPLAT-B, BIPLAT) CIP and the system clocks (SYSCK-A, SYSCK-B, SYSCK-C) of the system clock generating means 60 and the 864 kHz clock as inputs to the BIP reset clocks (BIPRES-A, BIPRES-B, BIPRES). BIP reset causing -C) BIP test circuit, characterized in that consisting of a clock generating means (50). 2. The BIP comparison means (20) according to claim 1, wherein the BIP comparison means (20) inputs a 2-bit BIP value calculated by being connected to an output terminal of the BIP value generating means (10) and a 2-bit BIP value extracted from the TUG21 signal. A BIP inspection circuit comprising first and second exclusive OR means (100,101). 3. The first and second BIP generating means (70, 71) are the output of the fifth and sixth exclusive logical sum means (85,86) and the BIP clock (BIPCK-A, BIPCK-B, BIPCK) Negative logic means 91 for inputting C, first inverter means 92 for inverting the reset signal RESETB, and the BIP reset clocks BIPRES-A, BIPRES-B, and BIPRES-C. Inverting second inverter means 93, logical multiplication means 94 for inputting the outputs of the first and second inverter means 92, 93, and negative logical multiplication means 91 and logical multiplication means 94 A first D flip-flop 95 connected to an output terminal of the negative logic unit 91 and the logical multiplication unit 94 and the system clocks SYSCK-A, SYSCK-B and SYSCK-C. And an output terminal of the first D flip-flop 95 and the first inverter means 92, the output of the first D flip-flop 95 and the first inverter means 92, and the BIP latch clock ( 2nd DFL input with BIPLAT-A, BIPLAT-B, BIPLAT-C) BIP test circuit being configured to flop 96. 4. The BIP latch clock generating means (40) according to claim 3, wherein the BIP latch clock generating means (40) outputs a BIP latch clock (BIPLAT-A) using the BIP clock (BIPCK-B) as a clock input and a 2 kHz clock (OTUV5B1) as a data input. Outputs the first D flip-flop 41 and the first D flip-flop 41 as data inputs, and outputs the BIP latch clock BIPLAT-B using the BIP clock BIPCK-C as a clock input. A third D outputting the BIP latch clock BIPLAT-C using the output of the 2D flip-flop 42 and the output of the 2D flip-flop 42 as the clock input of the BIP clock BIPCK-A. BIP inspection circuit, characterized in that consisting of the flop flip (43). 4. The BIP reset clock generating means (50) according to claim 3, wherein the BIP reset clock generating means (50) comprises: first logical product means (54) and the first logic for inputting the system clock (SYSCK-B) and the BIP latch clock (BIPLAT-A); A first D flip-flop 51 for outputting the BIP reset clock BIPRES-A with the output of the multiplication means 54 as the data input and the 864 kHz clock as the clock input; the system clock SYSCK-C and the BIP The second logical multiplication means 55 having the latch clock BIPLAT-B as the input, the output of the second logical multiplication means 55 as the data input, and the 864 kHz clock as the clock input, the BIP reset clock BIPRES- A second D flip-flop 52 for outputting B), third logical multiplication means 56 for inputting the system clock SYSCK-A and BIP latch clock BIPLAT-C, and the third logical multiplication Consisting of a third flip-flop 53 which outputs the BIP reset clock BIPRES-C as the output data input of the means 56 and the 864 kHz clock as the clock input. BIP test circuit of Jing.