KR950005140B1 - No data detecting circuit of digital data repeating circuit - Google Patents

Abstract

This repeater implements the functions that are suitable for the Bell standard and KT MX13 standards. This no-data detecting circuit detects input signal and generates alarm signal and satisfies the alarm recovery condition. This repeater consists of the first interval clock IT1V(1), a data detecting block(24), an alarm signal generator(36), an alarm output and condition releasing block(44) that cuts off alarm signal to indicate signal(AIS) and out-of-frame signal(MS).

Description

No data detection circuit of digital data relay

1 is a no data detection circuit diagram used in a conventional digital data relay,

2 is a no data detection circuit diagram of a digital data relay device according to the present invention;

3 is a detailed connection diagram of the mux draw 12 and the latches 38 and 40 shown in FIG.

4 and 5 are operation timing diagrams of FIG.

The present invention relates to a no data detection circuit of a digital data transmission apparatus, and more particularly, to a no data detection circuit that detects a loss of an input signal and generates an alarm signal and satisfies a return condition.

In general, PCM multiplexing devices in digital data transmission devices require a no data detection circuit that detects no data when a data line is disconnected, short-circuited, or not transmitted from the other station. .

Such a no data monitoring circuit detects when a bipolar or unipolar data signal is not input for a certain period due to disconnection or short circuit in the PCM transmission line, and is important for generating a line alarm or a no data alarm. For example, the KT MX13 standard and the Bell standard define the alarm issuing conditions and return conditions when an input signal is lost as follows.

1) Alarm output condition when input signal is lost: "0" is continuously received or pulse is generated for more than 175 ± 75 bits or equivalent time to North America (NAS) DS1, European (CEPT) DS1, DS3 input signal. If not present, an input loss alarm should be declared before the demodulation of the AMI or B8ZS (NAS BS1) HDB3 (CEPT DS1), B3ZS (DS3) codes of the input signal, and corresponding to 250 bits of the input signal. Should be detected in time.

2) Return condition when the input signal is lost: The input DS3 signal is normal when the frame bit and the parity bit are normally received, the pulse density is 33% or more, and the stuffing control bits (C) are not all "1". Should be declared as

That is, the input signal return condition is when the frame of the input DS3 signal (within PEFRAMEC 2ms) is completed and the stuffing control bits are not all "1", which means that the DS3 input signal is stable as normal. Therefore, the input signal alarm trigger condition issues a loss alarm when the number of signals is maintained at "0" over 175 ± 75 bits, and the input signal return condition is a normal signal even if "0" within the input signal is within 175 ± 75 bits. If not, the input signal loss alarm (No Signal) shall not be released.

The conventional input loss detection circuit for achieving the alarm condition as described above uses a RC time constant using a resistor and a capacitor as shown in FIG. 1, and RC of the resistor R1 and the capacitor C1. The time constant value is input for 6 hours as long as "0" (ZERO) of 175 ± 75EA, and it is converted into a voltage to generate an alarm.

When there is a signal input from the outside in the circuit as shown in FIG. 1, a peak detection unit composed of diodes, resistors, and capacitors D1, R1, and C1 provides a constant "high" signal to a comparator (CP). Enter

At this time, the comparator CP compares the reference level of the lightning circuit formed with the resistors R2 and VR1 with the output of the peak detector, and when the input signal satisfies the above condition, the output is kept "high" and the alarm is not alarmed. Maintain state.

However, when the input signal is received at a lower level (state of No SIGNAL) than the time constant value composed of the resistor R1 and the capacitor C1, the inverting terminal (-) of the comparator CP is converted to "low". In this case, the comparator CP generates a no data alarm as "low" when it is low compared with the reference level.

However, the conventional circuit as shown in FIG. 1 has the following problems. First, use the resistor and the capacitor to generate an alarm that meets the input signal conditions (175 ± 75 pulse signals are continuously generated when the signal is input at the state of "0" (ZERO)) due to the error of the generator resistance and the capacitor. It is difficult to obtain the value, and secondly, it must be designed according to the alarm release condition (DS3 class MX13 standard), but the circuit configuration is impossible when applying KKT MX13 standard and Bell standard because the conventional circuit is configured as the alarm condition.

Therefore, an object of the present invention is to implement a function suitable for the bell standard and KT MX13 standard by detecting the loss of the input signal using a digital circuit. In other words, the present invention provides a no data detection circuit that detects a loss of an input signal and generates an alarm signal and satisfies an alarm return condition.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a no data detection circuit diagram according to the present invention, the configuration of which is as follows.

The first logic in the data stream input from the outside within the input period of the first Interval clock IT1V (1) having a predetermined period, for example, is detected by detecting a logic "0". The data detection unit 24 outputs a no data detection signal when a first logic is maintained for the first interval period, and the no data detection signal output from the data detection unit 24 is compared with the first interlock clock IT1V (1). An alarm signal generator 36 for delaying by the delayed second interlock clock IT1V (0) and generating an alarm signal by logically combining the delayed no data detection signal and the no data detection signal of the data detection unit 24; The alarm signal output from the alarm signal generator 36 is gated and output, and a normal alarm indication signal (AIS) indicating a return and an out-of-frame signal of a normal state are output. in response to an input of a frame (MS) It consists of an alarm output, and condition release portion (44) to block the output of the alarm signal.

In the above configuration of FIG. 2, reference numeral 52, which has not been described, is a gate circuit, which is a logic combination of a frame reset signal RSTF, an out-off frame signal MS, and an alarm display signal AIS to reset the reset signal. This circuit generates an alarm reset signal for releasing an alarm when the RSTF is "high", the out-off frame signal MS is "low", and the alarm display signal AIS is "high".

In the configuration of FIG. 1, the data detector 24 is reset by the input of the first interlock clock IT1V (1), and latches the data DATA input to the terminal D by the input of the reception clock RCLK. A multiplexed latch 10 to be output and an output of the mux latch 10 are input to the terminal T1, and a current output state signal output from its output terminal Q1 is output to the terminal D1. Mux draw which selects one of the signals input to the two terminals D1 and T1 by the inversion signal of the current output state and latches the selected signal by the inversion logic of the clock RCLK. (12) and the terminal D2 are connected to the output terminal Q1 of the mux draw 12, and the input signal is latched by the second interlock clock IT1V (0) and output as a no data detection signal. It consists of a latch 18. Here, each of the mux draw (10, 12) is composed of a multiplexer and a D-type flip-flop for selecting one of the signals input to the two input terminals by the input of the selection signal, the operation thereof will be described later Will be elucidated by the explanation of FIG.

The alarm signal generator 36 shifts and delays the no data detection signal output from the latch 18 by the second interlock clock IT1V (0), the output of the shift register and the latch ( 18) outputs the NAND gate 32 and the output of the NAND gate 32 by negatively multiplying the no-data detection signal outputted from 18) and inverting the gate signal when the two signals are the no-data detection logic to output an alarm signal. It consists of a latch 33 latched by IT1V (0). In this shift register, three D-type latches 26, 28, and 30 are connected in series, and the reset signal RSTF and the signal of the output terminal Q2 of the above-described mux draw 12 are negatively summed. To reset the D-type latches 26, 28, and 30.

The alarm signal and condition release unit 44 shown in FIG. 2 includes two latches 38 and 40 for delaying the alarm signal output from the latch 33 and generating an alarm condition signal. And a gate 42 which multiplies the alarm condition signal outputted from 40 and the alarm signal outputted from the latch 33 and outputs the alarm signal to the outside. At this time, the two latches 38 and 40 are connected as follows. The clock terminal CP5 of the latch 38 is connected to the output terminal Q4 of the latch 33, and the clock terminal CP6 of the latch 40 is connected to the output terminal Q5 of the latch 38. It is composed.

The gate circuit 52 inverts the inverters 46 and 48 which inverts the out-off frame signal MS and the reset signal RSTF, respectively, and the outputs of the inverters 46 and 48 and the alarm display signal. It consists of the AND gate 50 which logically multiplies (AIS) and sets the latches 38 and 40 to set an alarm condition.

FIG. 3 shows the configuration of the latches 38 and 40, which are dividers connected to the mux draws 10 and 12 in the second diagram. (A) shows the configuration of the mux draw 12, and is composed of a 2x1 multiplexer (MUX) and a latch (D F / F). The multiplexer MUX selects and outputs a signal input to the terminal D when the signal input to the terminal SE is “low”, and selects and outputs a signal input to the terminal T when the signal is “high”. do.

(B) shows an example of connecting the D flip-flop in the form of a divider. Accordingly, it can be seen that the latches 38 and 40 divide the signal input to the clock terminal into two divisions and output the divided signals. For example, when the clock signal CLK inputted to the clock terminal is changed to "low", the output is converted by outputting the output of the inverted output terminal so that there is an input of "low".

4 and 5 are operational waveform diagrams of FIG. 2, FIG. 4 is an operational waveform diagram of the data detector 24, and FIG. 5 is an operational waveform diagram of the alarm signal generator 35. As shown in FIG.

An operation example of FIG. 2 according to the present invention will now be described with reference to FIGS. 3, 4, and 5.

When the reset signal RETF in the "high" state is input as shown in FIG. 4C, all circuits of FIG. 2 are reset and initialized. When initialized, the latches 38 and 40 in the alarm signal and condition release section 44 are inverted by the inverter 48 and signaled "high" by the signal "low" output from the AND gate 50. It supplies to the AND gate 42, respectively.

In this reset state, when the clock RCLK and the data DATA as shown in FIGS. 4A and 4B are input, the mux draw 10 converts the input data DATA to the clock RCLK. The latch is input to the mux draw 12. At this time, the first interlock clock IT1V (1) as shown in FIG. 4 is input to the reset terminal R of the mux draw 10 and the mux draw 12 through the NOA gate 16. The first interlock clock IT1V (1) is input in a 34-bit period based on the input clock. Accordingly, the mux draw 10 and the mux draw 12 check the input data DATA as shown in FIG. 4 (A) by 34 bits by the first interlock clock IT1V (1). If any of the 34 bits of the data DATA is " high " is input, the mux draw 12 is output as " high ". However, if all 34-bit input data is "0", the output of the mux draw 12 is "low" as shown in FIG. Accordingly, the mux draw 10 and 12 have a function of checking the presence or absence of input data DATA in a 34-bit unit and sending the result to the latch 18.

At this time, the latch 18 latches and outputs the signal output from the mux draw 16 as shown in FIG. 4 (G) by the first interlock clock IT1V (1). Accordingly, the data detector 24 checks the input data DATA in a 34-bit period, and when the first logic, for example, "0" is continuously input, outputs a no data detection signal that becomes "high" as shown in FIG. It is provided as an input of the NAND gate 32 and the latch 26 of the alarm signal generator 36. Here, reference numeral 20 denotes a buffer that buffers a signal of digital logic.

On the other hand, the latches 36 to 30 in the alarm signal generator 36 transmit a no-data detection signal as shown in FIG. 4 (H) or FIG. 5 (d) to the second interlock clock IT1V of FIG. 5 (b). By input of (0), it inputs to the NAND gate 32 by 3-step delay delay like FIG. 5 (e, f, g). When the data input to the mux draw 10 during the operation as described above has a value of logic "1", the output of the mux draw 12 is "high", which is inverted by the noah gate 34 When the data of logic "1" is input, the shift registers are reset. That is, it is checked from the data detector 24 whether the 34-bit × 4 = 136-bit consecutively continues the no data, and when the shift register detects “1” even in the case of 1 bit, the shift register muxdraws. It is automatically released by 12 and the noah gate 34. Therefore, the data detection unit 24 that checks 34 bits initially checks 34 bits four times in succession so that the total number of bits is checked based on 34 + 136 bits = 170 bits.

On the other hand, the NAND gate 32 has a fifth data (g) delayed output from the shift register and the no data detection signal output as shown in FIG. 5 (d) in the latch 18 of the data detector 24. The non-data detection signal is negatively multiplied so that when the two signals are " high " The latch 33 latches the alarm signal as shown in FIG. 5 (h) by the second interlock clock IT1V (0) as shown in FIG. 5 (b) as shown in FIG. 5 (i). Therefore, if the input data string is kept " low " for 175 cycles of the clock, an alarm signal of " low " such as FIG. 5 (k) is output through the AND gate 42. FIG.

As described above, when the latch 33 generates an alarm signal in the "low" state, the output of the latches 38 and 40 configured as shown in FIG. 3 (b) transitions from "high" to "low" to cancel the alarm. Will be prevented. When the loss of the input data is returned in the above alarm state, the output of the latch 33 returns from "low" to "high". However, the AND gate 42 continues to output an alarm signal of "low", which is maintained until the alarm release condition, that is, the output of the latches 38 and 40 is set to "high". That is, even if a signal of "1" is detected within a period of inputting 175 ± 75 pulses, the signal to be input is F.FRAME, which is a release cancel condition, and the valid parit bits and C-bits have the same value. No data alarm cannot be cleared because it is not 1 ").

In the no data alarm state as described above, when the above condition is satisfied and the signal of the neighboring off frame MS is changed from "low" to "high", the output of the inverter 46 and the output of the AND gate 50 are " Low ", and the latches 38 and 40 are set. When the latches 38 and 40 are set, the signal output to the output terminals Q5 and Q6 is converted to " high " so that the alarm of the no data is released.

As described above, according to the present invention, by configuring a no-data alarm circuit using a digital circuit, it is possible to detect accurate no-data satisfying the bell standard and the MX13 standard of KT, thereby improving the accuracy of the alarm processing and the reliability of the device. .

Claims (5)

In a no data detection circuit of a digital data relay, the first logic detected by detecting a first logic in a data string input from the outside within the input period of the first interlock clock IT1V (1) having a predetermined period is the above-mentioned. A data detector 24 for outputting a no-data detection signal by an input of a second interlock clock IT1V (0) delayed from the first interlock clock IT1V (1) during a first interval period; and the data detector 24 Is connected to an output terminal of the delayed output no data detection signal by the input of the second interlock clock IT1V (0), and the delayed no data detection signal and the no data detection signal of the data detection unit 24 are delayed. An alarm signal generator 36 for generating an alarm signal in logical combination and an output terminal of the alarm signal generator 36 for outputting the generated alarm signal, and indicating the return of data. Smiling off frame signal (MS) in response to the input digital data, no-data detection circuit, characterized in that consists of alarm output and condition release portion (44) to block the output of the alarm signal. 2. The data DATA of claim 1, wherein the data detector 24 is reset by the input of the first interlock clock IT1V (1) and is input to the terminal D by the input of the reception clock RCLK. Mux latch 10 for latch output and the output of the mux draw 10 to terminal T1, and the current output state signal output from its output terminal Q1 to terminal D1. A mux draw 12 for selecting one of the signals input to the two terminals D1 and T1 by the inversion signal of the current output state and latching the selected signal by the inversion logic of the clock RCLK. ) And a latch for connecting the terminal D2 to the output terminal Q1 of the mux draw 12 and latching the input signal by the second interlock clock IT1V (0) and outputting it as a no data detection signal ( 18) a no data detection circuit of a digital data relay device. The shift register according to claim 2, wherein the alarm signal generator (36) comprises: a shift register for shifting and delaying the no data detection signal output from the latch (18) by the second interlock clock (IT1V (0)); A NAND gate 32 which negatively multiplies the output of the register and the no data detection signal output from the latch 18 and inverts the gate signal when the two signals are the no data detection logic to output an alarm signal, and the NAND gate 32. And a latch (33) for latching the output of the output by the second interlock clock IT1V (0) and outputting the alarm signal as an alarm signal. 4. The no-data detection circuit according to claim 3, wherein the shift register has three flip-flops connected in series and delays the input by the second interlock clock IT1V (0). 4. The digital data transmission as claimed in any one of claims 1 to 3, wherein each of the first and second interlock clocks IT1V (1) and IT1V (0) is a clock having a 34-bit period of input data. No data detection circuit of the device.