KR0150237B1 - Synchronous transmission system framing byte error detector - Google Patents

Abstract

The present invention receives the frame-synchronized STM-1 or STM-4 signal and converts it into a low-speed parallel signal, calculates a BIP-8 code only for the framing bytes, and calculates the BIP-8 so far in the non-framing bytes. Keep the code intact and calculate the BIP-8 code continuously from the next received framing byte, and when the register is read by an external CPU, the calculated BIP-8 code value up to that point is the data bus. The code generator, which is sent to and generates a BIP-8 code, is about a framing byte error detector in a synchronous transmission system that clears and computes a new BIP-8 code from the next received framing byte, until the next time this register is read. During the period of time, transmission errors in the framing bytes can be identified using a single register. There is an advantage.

Description

Framing Byte Error Detector in Synchronous Transmission System

1 is a framing byte error detector according to the present invention.

2 is a BIP-8 code generation timing diagram for a byte stream.

* Explanation of symbols for main parts of the drawings

1: code generator 2: comparator

3: AND gate 4: edge detector

The present invention relates to a framing byte error detector of a synchronous transmission system, and more particularly, converts high-speed bit data into low-speed parallel data, and then performs bit interleaved parity (BIP) -8 calculation. A framing byte error detector that effectively monitors the status of a byte transfer.

Framing bytes for frame synchronization are allocated to signals having a frame structure. Currently, ITU-T recommends declaring 00F (Out Of Frame) if an error occurs in the framing bytes continuously for 626 ms. However, there is no particular recommendation for the transmission performance monitoring method for intermittent framing byte errors of 625 ms or less. In order to monitor the transmission status of the framing bytes, three A1 bytes and three A2 bytes must be identified in the 155 Mbps Synchronous Transport Module level-1 (STM-1) structure, and 12 each in the 622 Mbps STM-4 structure. You should check the A1 byte and A2 byte of. In other words, to check the framing bytes of the STM-1 or STM-4 signal transmitted in the byte stream, 155 Mbps STM-1 requires six monitoring registers for three A1 bytes and three A2 bytes. In the case of the STM-4, only 24 watch registers are needed to watch the framing bytes.

In the present invention, a method for efficiently detecting framing byte errors of 625 ms or less in STM-1 and STM-4 signals, converting the framing bytes into a low-speed parallel signal, and then using a BIP-8 code. Registers also provide circuitry to effectively monitor the transfer status of the framing bytes.

1 shows a configuration of a framing byte error detector according to the present invention.

Referring to FIG. 1, the framing byte error detector of the present invention includes an edge detector 10 that detects a rising edge after a read operation of a corresponding register is completed, and a framing byte DATA [7] input in parallel. 0]), a code generator 20 for calculating parallel BIP-8 codes, a pattern comparator 30 for comparing the output of the code generator 20 with the patterns of '00000000' and '11011110', and The AND gate 40 receives and outputs the output of the code generator 20 and the output of the pattern comparator 30.

Referring to the basic operating principle of the present invention having such a configuration as follows. Receives the frame-synchronized STM-1 or STM-4 signal, calculates the BIP-8 code only for the framing bytes, and keeps the BIP-8 code calculated so far in the non-framing bytes. Compute the BIP-8 code continuously from the framing bytes. When the register is read by an external central processing unit, the calculated BIP-8 code value up to that time is sent to the data bus, and the code generator 20 generating the BIP-8 code is cleared and at the next received framing byte. Calculate the new BIP-8 code. This allows the use of a single register to identify transmission errors in the framing bytes during the time period until this register is next read.

The edge detector 10 includes a NOR gate 11 that receives a chip select signal CSB and a read signal RDB from an external central processing unit (not shown), and an output of the NOR gate 11. A first D flip-flop 12 connected to the input terminal D, a second D flip-flop 13 connected to the output terminal Q of the flip flop 12, and a first D- flip flop 13; Inverted output of flip-flop 12 ( ) And a first NAND gate 14 connected to an output terminal Q of the 2D flip-flop 13 and outputting a selection control signal SEL. The edge detector 10 generates a pulse having a state of '0' and having a clock width immediately after the read operation when the external CPU reads the register. This pulse is provided as its select control signal SEL to the code generator 20 which will be described in detail below.

The code generator 20 has a second NAND gate 21 which receives the parallel data signal DATA [7: 0] and the framing byte position indication signal EN, the selection control terminal S, and an 8-bit parallel. A third flip-flop 22 having two input terminals A and B for inputting a signal, an output terminal Q for delaying the input signal and an inverted output terminal QB, and having a multiplexing function; The terminal is connected to the output terminal of the second NAND gate 21, the other input terminal is connected to the inverted output terminal QB of the third flip flop 22, and its output terminal is one input terminal of the third flip flop. An X-OR gate 23 connected to (A) and an input terminal are connected to an output terminal of the second NAND gate 21, and its output terminal is connected to the other of the third flip-flop 22. Inverter 24 is connected to one input terminal (B).

In FIG. 1, DATA [7: 0] is STM-1 or STM-4 data in a frame-synchronized byte stream, and the EN signal is a value of '1' in the framing byte of DATA [7: 0]. Is a framing byte position indicating signal.

The second NAND gate 21 receives the STM-1 and STM-4 data and the framing byte position indication signal EN inputted through DATA [7: 0], and when the EN signal is '1', DATA [7] Outputs the inverted signal of: 0] and outputs '11111111' when the EN signal is '0'.

The third flip-flop 22 is a flip-flop having a multiplexing function. The third flip-flop 22 receives a signal input to any one of the two input terminals A and B according to the state of the selection control signal SEL input to the selection terminal S. Select to output from the up edge of the clock.

The exclusive or gate 23 receives the output of the second NAND gate 21 and the inverted output of the third flip-flop 22 and performs an exclusive OR to perform X-ORing on the first flip-flop 22. Provided to input terminal (A).

The inverter 24 inverts the output of the second NAND gate 24 and provides it to the second input terminal B of the third flip-flop 22.

The third flip-flop 22 selects an input signal input through its second input terminal B when the selection control signal SEL from the first NAND gate 14 is '0', thereby upwardly increasing the clock. When the selection control signal SEL is '1', the output signal is output at the edge and the output signal is selected at the upstream edge of the clock by selecting the input signal input through its first input terminal A.

The pattern comparator 30 receives the output of the third flip-flop 22, compares the predetermined patterns '00000000' and '11011111', and outputs '0' when it matches and outputs '1' when it does not match.

The AND gate 40 outputs the output of the third flip-flop 22 as it is when the output of the pattern comparator 30 is '1', and outputs '00000000' when the output of the pattern comparator 30 is '0'. Output

2 is a timing diagram of inputting an EN signal indicating a frame-synchronized STM-1 data and a framing byte section to calculate a BIP-8 code with respect to the framing byte. A framing byte A1 (= 11110110) for a 155 Mbps STM-1 signal is shown in FIG. ) And three A2 (= 00101000) are allocated. When the selection control signal SEL is '0', 11110110 of DATA [7: 0] is selected and output from the up edge of the clock through the output terminal Q of the third flip-flop 22, and its inverted output ( QB) is input to the exclusive NOR gate 23, and is again input to the first input terminal A of the third flip-flop 22 and output through the output terminal Q at the up edge of the clock. The output Q of the third flip-flop 22, which is the result of the repetitive operation on the framing byte of STM-1, becomes the BIP-8 code for the framing byte of the STM-1 signal. The BIP-8 code for the framing byte of STM-1 has a value of 11011111 in odd frames and 00000000 in even frames when it is normal. In addition, in the 622Mbps STM-4 signal, since the framing bytes are allocated 12 A1 (= 11110110) bytes and 12 A2 (= 00101000) bytes, the BIP-8 code for a normal framing byte is always 00000000. If an error occurs during the transmission of the framing bytes, the BIP-8 code will be a different value. Therefore, the occurrence of a transmission error for a framing byte of an STM-1 or STM-4 signal can be monitored using a single register between specific time intervals when the corresponding register is read by an external CPU. Parallel BIP-8 calculation to check transmission status, perform network operation efficiently and actively, convert high speed bit data into low speed byte data and then calculate parity for low speed byte data The use of a circuit has the advantage that high-speed data can be monitored using a low cost device.

Claims (3)

An edge detector 10 for detecting an up edge after the read operation of the corresponding register is completed, a code generator 20 for calculating a BIP-8 code for a framing byte input in parallel, and an output of the code generator 20 Includes a pattern comparator 30 that compares a pattern with patterns of '00000000' and '11011110', and an AND gate 40 that receives and logically multiplies the output of the code generator 20 and the output of the pattern comparator 30. Framing byte error detector in the transmission system. The NOR gate of claim 1, wherein the edge detector 10 receives an NOR gate 11 that receives a chip select signal CSB and a read signal RDB from an external source, and an input terminal to an output of the NOR gate 11. A first flip-flop 12 to which (D) is connected, a second flip-flop 13 to which an input end D is connected to an output terminal Q of the first flip-flop 12, and the first flip-flop (12) inverting output stage ( ) And a framing byte error of a synchronous transmission system including a first NAND gate 10 connected to an output terminal Q of the second flip-flop 13 and outputting a selection control signal SEL. Detector. 2. The code generator (20) according to claim 1, wherein the code generator (20) has an 8-bit parallel with a second NAND gate (21) for receiving a parallel data signal (DATA [7: 0]) and a framing byte position indication signal (EN). Two input terminals A and B for inputting a signal, an output terminal Q for delaying and outputting the input signal, an inverted output terminal QB, and the selection control signal SEL from the edge detector 10 A third flip-flop 22 having an input selection control terminal S and having a multiplexing function; one input terminal is connected to an output terminal of the second NAND gate 21, and the other input terminal is the third flip-flop. An exclusive-or (X-OR) gate 23 connected to the inverting output terminal QB of the flop 22 and its output terminal connected to one input terminal A of the third flip-flop; An input terminal is connected to an output terminal of the second NAND gate 21, and its output terminal is the other of the third flip-flop 22. Framing byte error detector of a synchronous transmission system including an inverter (24) connected to the output terminal (B).