KR920005365B1 - Nrz/cmi(iii) code conversion circuit - Google Patents

Abstract

The apparatus includes a first D flip-flop (U1) for receiving NRZ data and synchronizing clock pulses to re-time them. An OR gate (U3) receives the output of the first D flip-flop (U1) and the synchronizing clock pulses to logic-add them and to generate space segment pulses. A first exclusive OR gate (U4) exclusively logic- adds the outputs of the first and second D flip-flop (U1)(U2) , and the second D flip-flop (U2) receives the synchronizing clock pulses of the NRZ data to alternately pick up only mark bits. A second exclusive OR gate (U5) exclusively logic-adds the outputs of a delay device (U6) and the second D flip-flop (U2), thereby outputting code pulses.

Description

NRZ / CMI (II) code conversion device

1 is a block diagram of a code conversion device according to the present invention.

2 is a circuit diagram of an embodiment of a code conversion device according to the present invention.

(A) and (b) of FIG. 3 are timing diagrams for the respective circuit parts of FIG.

* Explanation of symbols for main parts of the drawings

1: Retiming unit 2: Space bit generation and delay unit

3: Alternating mark bit generator 4: CMI (II) code generator

U1, U2: D flip-flop U3: OR gate

U4, U5: exclusive OR gate U6: delay element

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for converting a non-return to zero (NRZ) type data bit string into a code mark inversion (CMI) code. In particular, the present invention relates to an apparatus for converting an NRZ type bit string into a CMI (II) (Code Mark Inversion Class II) code.

Code Mark Inversion Class I (CMI) code, which is widely used when the transmission speed is around 100 Mbps in a conventional optical transmission system, has problems such as timing slip and baseline shaking, despite various advantages. (I) Code Mark Inversion Class II (CMI) code, which makes use of the advantages of code and compensates for the above disadvantages, is known to be useful in not only synchronous transmission but also asynchronous transmission because of easy phase synchronization. However, compared to the CMI (Ⅰ) coder, the implementation of the CMI (II) coder is difficult, and it is difficult to realize the practical duty cycle of the CMI code pulse.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and uses a simple logic device to glitch a CMI (II) code pulse that may be generated in the process of converting an NRZ data bit string into a CMI (II) code pulse. NRZ / CMI (II) code conversion that facilitates the practical use of transmission system using CMI (II) code by keeping the duty cycle accurate, and improves the error monitoring function of transmission system using CMI (II) code. It is an object of the present invention to provide a device.

In order to achieve the above object, the present invention provides a retiming means for retiming an input NRZ data bit string to a clock synchronized with the same; a space for synthesizing a space bit of the input NRZ data bit string and a transmission clock and performing an appropriate time delay. Bit generating and delaying means, alternating mark bit generating means for alternating only mark bits in a retimed NRZ data bit string, and CMI (II) code generating means for converting input NRZ data into a CMI (II) code. A code conversion device comprising: A 1D flip-flop for inputting NRZ data through a data input terminal and retiming a synchronous clock pulse of the NRZ data through a clock pulse input terminal, a synchronous clock pulse of the output of the 1D flip-flop and the NRZ data And OR for two input signals, OR for generating a pulse representing a space bit section, a time delay element connected to an output terminal of the OR gate, an output of the first 1D flip-flop, and a 2D flip-flop A first exclusive OR gate that performs an exclusive OR on the output of the input signal, an output of the first exclusive OR gate through a data input terminal, and a synchronous clock pulse of the NRZ data as a clock pulse input terminal. A 2D flip-flop that alternates and outputs only the Mark bits at < RTI ID = 0.0 > and < / RTI > two input signals connected to output terminals of the delay element and the 2D flip-flop. And a second exclusive OR gate that outputs a CMI (II) code pulse by performing exclusive OR on the call.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of the present invention. As shown in the drawing, a retiming unit 1 for retiming input NRZ data and a space connected to an output terminal of the retiming unit 1 are shown. A bit pulse generation and delay unit 2, an alternating mark bit generator 3 connected to the output terminal 2 of the retiming unit 1, a space between the alternating mark bit generator 2, and a space And a CMI (II) code generator 4 which is connected to an output terminal of the bit pulse generator and delay unit 3 and outputs a CMI (II) code pulse.

2 is a circuit diagram of an embodiment of a code conversion device according to the present invention, which encodes an NRZ data bit string into a CMI (II) code at a clock pulse of the same frequency as the NRZ data bit rate. In the figure, U1 and U2 are D flip-flops, U3 is an OR gate, U4 and U5 are an exclusive OR gate, and U6 is a delay element. The D flip-flop U inputs NRZ data to the data input terminal D1 and reclocks the NRZ data by inputting a clock pulse synchronized with the bit string of the NRZ data to the clock pulse input terminal CP1. do. The OR gate U3 having one input terminal connected to the output terminal Q1 of the D flip-flop U1 has an input of the output of the D flip-flop U1 and the synchronization pulse C of the NRZ data as two inputs, and is spaced ( Space) Synthesize and output clock pulses only in the bit section. The output is also input to one input terminal of the 2-input exclusive OR gate U5 of the output terminal through a time delay element U6 connected to the output terminal of the OR gate U3. A two-input exclusive OR gate U4 is connected to the output terminal Q2 of the D flip-flop U1 and the output terminal Q2 of the D flip-flop U2 to re-time the NRZ data and the D flip-flop U2. An exclusive OR is performed on the current state of Q2 to generate an alternating signal each time the mark bit is input, and outputs the alternating signal to the data input terminal D2 of the D flip-flop U2. The D flip-flop U2 inputs the output of the exclusive OR gate U4 through the data input terminal D2 and kicks the clock pulse C in synchronization with the NRZ data bit string input to the clock pulse input terminal CP2. Transition to state An exclusive OR gate U5 is connected to the delay element U6 and the D flip-flop U2 to convert the synthesized pulses of the space bits and clock pulses of the NRZ data and the alternating mark bits into CMI (II). Output the data pulse string.

As described above, the operating principle of the present invention is as follows. When the NRZ data bit string synchronized to the clock pulse having the same frequency as the CMI code data transmission bit rate is input to the data input terminal D1 of the D flip-flop U1, the input NRZ data bit string is retimed to a clock pulse to clock the clock. Limiting the amount of change in the relative delay time of the data to the pulses within the D flip-flop (U1) delay time and then ORing this retimed NRZ data bit string (Q1 of U1) with the input clock pulse, only the space bit section of the NRZ data bit string The clock pulses are synthesized and the mark bit section outputs a signal in which the mark state is maintained. Meanwhile, a signal obtained by exclusively ORing the signals of the retimed NRZ data bit string (Q1 of U1) and the data output terminal Q2 of the D flip-flop U2 is fed back to the data input terminal D2 of the D flip-flop U2. When the clock pulse inputted to the clock pulse input terminal CP2 of the D flip-flop U2 is synchronized with the NRZ data, an alternating mark signal, i.e., divided by two, is input every time a micro bit of the NRZ data bit string is input. The mark bit status signal (Q2 of U2) is output. Exclusive and OR of the alternating mark bit signal (Q2 of U2) and the alternating signal of the space bit and the clock pulse (the output signal of U3) causes the mark bit to alternate in the mark bit section of the NRZ data bit string and the clock pulse in the space bit section. A synthesized signal, that is, a signal obtained by converting a NRZ data bit string into a CMI (II) code is output.

(A) and (b) of FIG. 3 are timing diagrams for the circuit parts of FIG. 2 showing the case where the mark state and the space state appear three times in succession, two times in succession, and one in time, respectively. It can represent all the cases that can occur in the process of converting the data bit string to the CMI (II) code.

In the figure, (1) is NRZ data, (2) is clock pulse (C), (3) is output Q1 of D flip-flop U1, and (4) is space bit pulse C of OR gate U3. (5A), (6A) and (7A) are timing charts when the initial state of the D flip-flop U2 is "0" (low), that is, when Q2 = "0". 5A is a D flip-flop U2 output Q2, 6A is a signal applied to the data input terminal D2 of the D flip-flop U2, and 7A is an output CMI of the exclusive OR gate U5. II) Code pulse (Y), where Y = (Q1 + C) + Q2 can be expressed mathematically. (5B), (6B) and (7B) are timing charts when the initial state of the D flip-flop U2 is "1" (high), that is, Q2 = "1", and (5B) is a D flip-flop. The outputs (Q2) and (6B) of (U2) are the signals input to the data input terminal (D2) of the D flip-flop (U2), (7B) is the output CMI (II) code pulse (Y) of the exclusive OR gate (U6). ) And is expressed by the formula = (Q1 + C) + Q2.

As described above, the present invention alternates the mark bits of the NRZ data to a mark-space or a space-mark state, directly synthesizes the space bits with the transmission clock, and then synthesizes the alternating mark bits and the synthesized space bit pulses again to obtain CMI (II). ) And the mark bits and space bits of the NRZ data bit stream are independently processed during the same time to generate CMI (II) codes, thereby reducing the number of constituent logic elements and minimizing the gate delay to minimize timing glitches. The amount of change in the sign pulse width (clock pulse period T and half period T / 2) is kept to a minimum.

The present invention as described above has the following effects.

First, the CMI (II) coding function is implemented using simple logic elements.

Second, CMI encoding uses clock pulses of the same frequency as the NRZ data rate.

Third, since it is composed of simple logic elements, it is easy to integrate high-speed circuits.

Fourth, the amount of change in the pulse width of the CMI (II) code is small, so that the error rate can be reduced.

Claims (1)

Retiming means for retiming the input NRZ data bitstream to a clock synchronized with this; A code conversion device comprising: alternating mark bit generating means for alternating only mark bits in an NRZ data bit string; and CMI (II) code generating means for converting input NRZ data into a CMI (II) code; 1D flip-flop U1 for inputting NRZ data through the data input terminal D1, and retiming a synchronous clock pulse of the NRZ data through a clock pulse input terminal CP1, and the 1D flip-flop ( OR gate U3 for inputting the output Q1 of U1 and the synchronous clock pulse C of the NRZ data and ORing the two input signals to generate a pulse representing a space bit section, and OR gate A first exclusive OR that performs exclusive OR on the time delay element U6 connected to the output terminal of U3 and the output Q1 of the first D flip-flop U1 and the output Q2 of the second D flip-flop U2 An output of the first exclusive OR gate U4 is input through a gate U4 and a data input terminal D2, and a synchronous clock pulse of the NRZ data is input to a clock pulse input terminal CP2 to receive an NRZ data bit. 2D flip-flop U2 for alternately outputting only Mark bits in a column, and An NRZ / CMI (II) code conversion device.

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