GB1281390A - Testing digital data transmission systems - Google Patents
Testing digital data transmission systemsInfo
- Publication number
- GB1281390A GB1281390A GB6031469A GB6031469A GB1281390A GB 1281390 A GB1281390 A GB 1281390A GB 6031469 A GB6031469 A GB 6031469A GB 6031469 A GB6031469 A GB 6031469A GB 1281390 A GB1281390 A GB 1281390A
- Authority
- GB
- United Kingdom
- Prior art keywords
- bit
- register
- receiver
- bits
- data transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/24—Testing correct operation
- H04L1/242—Testing correct operation by comparing a transmitted test signal with a locally generated replica
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/24—Testing correct operation
- H04L1/241—Testing correct operation using pseudo-errors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
1281390 Error detection POST OFFICE 28 Oct 1970 [10 Dec 1969] 60314/69 Heading H4P In a system for testing a digital data transmission system a serial test pattern is transmitted in which each bit is generated as a function of two or more preceding bits, each spaced from the bit by a particular spacing, and a receiver of the pattern compares each bit with the corresponding two or more preceding bits to ascertain if the function is still satisfied, lack of correlation generating an error signal. The test pattern is generated by a shift register having the output of two stages, which may or may not be adjacent, modulo-2 added and fed back to the input of the register. At the receiver the arriving pattern is put in a register and each bit on entering is compared with the output of two stages ahead, spaced by the appropriate amounts. Since each erroneous bit, unless adjacent to other erroneous bits, gives rise to three error conditions on its passage through the receiver register, the count of error signals is divided by three or alternatively a modulo-2 adder is placed after the first stage of the receiver register to correct the erroneous bits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB6031469A GB1281390A (en) | 1969-12-10 | 1969-12-10 | Testing digital data transmission systems |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB6031469A GB1281390A (en) | 1969-12-10 | 1969-12-10 | Testing digital data transmission systems |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1281390A true GB1281390A (en) | 1972-07-12 |
Family
ID=10485419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB6031469A Expired GB1281390A (en) | 1969-12-10 | 1969-12-10 | Testing digital data transmission systems |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB1281390A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7412640B2 (en) | 2003-08-28 | 2008-08-12 | International Business Machines Corporation | Self-synchronizing pseudorandom bit sequence checker |
-
1969
- 1969-12-10 GB GB6031469A patent/GB1281390A/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7412640B2 (en) | 2003-08-28 | 2008-08-12 | International Business Machines Corporation | Self-synchronizing pseudorandom bit sequence checker |
| US7757142B2 (en) | 2003-08-28 | 2010-07-13 | International Business Machines Corporation | Self-synchronizing pseudorandom bit sequence checker |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| 435 | Patent endorsed 'licences of right' on the date specified (sect. 35/1949) | ||
| PCNP | Patent ceased through non-payment of renewal fee |