KR960009990B1 - Method for forming a dielectric layer in semiconductor device - Google Patents
Method for forming a dielectric layer in semiconductor device Download PDFInfo
- Publication number
- KR960009990B1 KR960009990B1 KR93012336A KR930012336A KR960009990B1 KR 960009990 B1 KR960009990 B1 KR 960009990B1 KR 93012336 A KR93012336 A KR 93012336A KR 930012336 A KR930012336 A KR 930012336A KR 960009990 B1 KR960009990 B1 KR 960009990B1
- Authority
- KR
- South Korea
- Prior art keywords
- dielectric layer
- forming
- semiconductor device
- polysilicon layer
- planarization
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 3
- 239000004065 semiconductor Substances 0.000 title 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 3
- 229920005591 polysilicon Polymers 0.000 abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR93012336A KR960009990B1 (en) | 1993-06-30 | 1993-06-30 | Method for forming a dielectric layer in semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR93012336A KR960009990B1 (en) | 1993-06-30 | 1993-06-30 | Method for forming a dielectric layer in semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950002017A KR950002017A (ko) | 1995-01-04 |
KR960009990B1 true KR960009990B1 (en) | 1996-07-25 |
Family
ID=19358550
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR93012336A KR960009990B1 (en) | 1993-06-30 | 1993-06-30 | Method for forming a dielectric layer in semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960009990B1 (ko) |
-
1993
- 1993-06-30 KR KR93012336A patent/KR960009990B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR950002017A (ko) | 1995-01-04 |
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Legal Events
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GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20090624 Year of fee payment: 14 |
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LAPS | Lapse due to unpaid annual fee |