KR950026114A - 반도체 소자의 데이타 출력버퍼 - Google Patents

반도체 소자의 데이타 출력버퍼 Download PDF

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Publication number
KR950026114A
KR950026114A KR1019940002244A KR19940002244A KR950026114A KR 950026114 A KR950026114 A KR 950026114A KR 1019940002244 A KR1019940002244 A KR 1019940002244A KR 19940002244 A KR19940002244 A KR 19940002244A KR 950026114 A KR950026114 A KR 950026114A
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KR
South Korea
Prior art keywords
data output
semiconductor device
potential
output buffer
output
Prior art date
Application number
KR1019940002244A
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English (en)
Other versions
KR960013859B1 (ko
Inventor
권정태
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940002244A priority Critical patent/KR960013859B1/ko
Priority to US08/383,005 priority patent/US5508635A/en
Priority to JP7017752A priority patent/JP2824405B2/ja
Priority to DE19503964A priority patent/DE19503964B4/de
Publication of KR950026114A publication Critical patent/KR950026114A/ko
Application granted granted Critical
Publication of KR960013859B1 publication Critical patent/KR960013859B1/ko

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106Data output latches

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

본 발명은 반도체 소자의 데이타 출력버퍼에 관한 것으로, 고전위(High)상태 출력시 정전압 발생기(voltage Regulator)로 부터 발생되는 데이타 출력전압(Voh)을 기준전압(Vref)과 같게 유지시키므로써 외부 동작전압의 변화에 무관하게 출력전압의 전위를 일정하게 하여 데이타 변화시 파워라인(Power Line)에 발생되는 노이즈(Noise)를 줄일 수 있도록한 반도체 소자의 데이타 출력버퍼에 관해 기술된다.

Description

반도체 소자의 데이타 출력버퍼
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 첨부된 도면은 본 발명에 따른 반도체 소자의 데이타 출력버퍼의 상세 회로도.

Claims (3)

  1. 반도체 소자의 데이타 출력버퍼에 있어서, 데이타 출력버퍼의 출력단자(Dout)의 전위와 기준전압 발생기(4)의 출력전위를 비교하는 전압 비교기(1)의 출력신호에 따라 데이타 출력버퍼의 출력단자(Dout)의 전위가 결정되고, 출력단자(Dout)의 전위가 일정전위 이상에서는 외부 동작전압의 변화와 무관하게 정전압 발생기(2)의 출력전위로 유지되도록 구성되는 것을 특징으로 하는 반도체 소자의 데이타 출력버퍼.
  2. 제1항에 있어서, 상기 정전압 발생기(2)는 센스 증폭기로부터의 독출 데이타가 “High”상태일때만 인에이블되도록 구성되는 것을 특징으로 하는 반도체 소자의 데이타 출력버퍼.
  3. 제1항에 있어서, 상기 센스증폭기로부터의 독출 데이타(Do)가 “High”상태일때 상기 출력단자(Dout)의 전위를 점차 높이기 위하여 상기 전압 비교기(1)의 출력이 설정된 시간동안 차단되도록 구성되는 것을 특징으로 하는 반도체 소자의 데이타 출력버퍼.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940002244A 1994-02-07 1994-02-07 반도체 소자의 데이타 출력버퍼 KR960013859B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019940002244A KR960013859B1 (ko) 1994-02-07 1994-02-07 반도체 소자의 데이타 출력버퍼
US08/383,005 US5508635A (en) 1994-02-07 1995-02-03 Reduced noise data output buffer with output level regulation
JP7017752A JP2824405B2 (ja) 1994-02-07 1995-02-06 半導体素子のデータ出力バッファ
DE19503964A DE19503964B4 (de) 1994-02-07 1995-02-07 Datenausgabepuffer einer Halbleitervorrichtung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940002244A KR960013859B1 (ko) 1994-02-07 1994-02-07 반도체 소자의 데이타 출력버퍼

Publications (2)

Publication Number Publication Date
KR950026114A true KR950026114A (ko) 1995-09-18
KR960013859B1 KR960013859B1 (ko) 1996-10-10

Family

ID=19376924

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940002244A KR960013859B1 (ko) 1994-02-07 1994-02-07 반도체 소자의 데이타 출력버퍼

Country Status (4)

Country Link
US (1) US5508635A (ko)
JP (1) JP2824405B2 (ko)
KR (1) KR960013859B1 (ko)
DE (1) DE19503964B4 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100411024B1 (ko) * 2001-06-29 2003-12-12 주식회사 하이닉스반도체 출력 회로

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09261031A (ja) * 1996-03-21 1997-10-03 Oki Micro Design Miyazaki:Kk 半導体集積回路の出力バッファ回路
US6018265A (en) * 1997-12-10 2000-01-25 Lexar Media, Inc. Internal CMOS reference generator and voltage regulator
US6255867B1 (en) 2000-02-23 2001-07-03 Pericom Semiconductor Corp. CMOS output buffer with feedback control on sources of pre-driver stage
US6404246B1 (en) 2000-12-20 2002-06-11 Lexa Media, Inc. Precision clock synthesizer using RC oscillator and calibration circuit
US8629697B2 (en) * 2012-06-01 2014-01-14 SK Hynix Inc. Semiconductor integrated circuit and method of operating the same
US10334193B2 (en) 2016-02-11 2019-06-25 Samsung Electronics Co., Ltd. Read-out circuits of image sensors and image sensors including the same
US10840907B1 (en) * 2019-11-19 2020-11-17 Honeywell International Inc. Source-coupled logic with reference controlled inputs

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4857765A (en) * 1987-11-17 1989-08-15 International Business Machines Corporation Noise control in an integrated circuit chip
JPH03219495A (ja) * 1990-01-24 1991-09-26 Sony Corp 出力回路
US5121013A (en) * 1990-02-12 1992-06-09 Advanced Micro Devices, Inc. Noise reducing output buffer circuit with feedback path
JP2922028B2 (ja) * 1991-08-30 1999-07-19 株式会社東芝 半導体集積回路の出力回路
US5184033A (en) * 1991-09-20 1993-02-02 Motorola, Inc. Regulated BiCMOS output buffer
US5367210A (en) * 1992-02-12 1994-11-22 Lipp Robert J Output buffer with reduced noise
US5248906A (en) * 1992-06-12 1993-09-28 Advanced Micro Devices, Inc. High speed CMOS output buffer circuit minimizes output signal oscillation and steady state current
JPH06112801A (ja) * 1992-09-29 1994-04-22 Hitachi Ltd 出力回路
KR0132504B1 (ko) * 1993-12-21 1998-10-01 문정환 데이타 출력버퍼
US5440258A (en) * 1994-02-08 1995-08-08 International Business Machines Corporation Off-chip driver with voltage regulated predrive
US5434519A (en) * 1994-10-11 1995-07-18 International Business Machines Corporation Self-resetting CMOS off-chip driver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100411024B1 (ko) * 2001-06-29 2003-12-12 주식회사 하이닉스반도체 출력 회로

Also Published As

Publication number Publication date
US5508635A (en) 1996-04-16
JP2824405B2 (ja) 1998-11-11
KR960013859B1 (ko) 1996-10-10
DE19503964B4 (de) 2006-04-13
DE19503964A1 (de) 1995-08-10
JPH0888558A (ja) 1996-04-02

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