KR940008261A - 바이씨모스(bicmos) 레벨 변환 회로 - Google Patents

바이씨모스(bicmos) 레벨 변환 회로 Download PDF

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Publication number
KR940008261A
KR940008261A KR1019930019279A KR930019279A KR940008261A KR 940008261 A KR940008261 A KR 940008261A KR 1019930019279 A KR1019930019279 A KR 1019930019279A KR 930019279 A KR930019279 A KR 930019279A KR 940008261 A KR940008261 A KR 940008261A
Authority
KR
South Korea
Prior art keywords
coupled
voltage level
emitter
signal
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019930019279A
Other languages
English (en)
Korean (ko)
Inventor
에이취. 팰리 3세 패리
가세미 헤임드
Original Assignee
빈센트 비, 인그라시아
모토로라 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 빈센트 비, 인그라시아, 모토로라 인코포레이티드 filed Critical 빈센트 비, 인그라시아
Publication of KR940008261A publication Critical patent/KR940008261A/ko
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
    • H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]
    • H03K19/017527—Interface arrangements using a combination of bipolar and field effect transistors [BIFET] with at least one differential stage

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
KR1019930019279A 1992-09-28 1993-09-22 바이씨모스(bicmos) 레벨 변환 회로 Withdrawn KR940008261A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US951,959 1992-09-28
US07/951,959 US5315179A (en) 1992-09-28 1992-09-28 BICMOS level converter circuit

Publications (1)

Publication Number Publication Date
KR940008261A true KR940008261A (ko) 1994-04-29

Family

ID=25492392

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930019279A Withdrawn KR940008261A (ko) 1992-09-28 1993-09-22 바이씨모스(bicmos) 레벨 변환 회로

Country Status (5)

Country Link
US (1) US5315179A (enExample)
EP (2) EP0794620A3 (enExample)
JP (1) JPH06204845A (enExample)
KR (1) KR940008261A (enExample)
DE (1) DE69315937T2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1236879B (it) * 1989-11-22 1993-04-26 Sgs Thomson Microelectronics Circuito elettronico comparatore
TW307064B (enExample) * 1993-09-08 1997-06-01 Advanced Micro Devices Inc
US5485106A (en) * 1994-04-05 1996-01-16 Sun Microsystems, Inc. ECL to CMOS converter
US5446400A (en) * 1994-11-07 1995-08-29 Motorola Inc. GTL compatible BICMOS input stage
US5502405A (en) * 1994-11-08 1996-03-26 Cypress Semiconductor Corporation Method and apparatus for CML/EC to CMOS/TTL translators
US5675809A (en) * 1995-02-10 1997-10-07 Ncr Corporation Voltage control circuit for a dual voltage bus computer system
US6600338B1 (en) * 2001-05-04 2003-07-29 Rambus, Inc. Apparatus and method for level-shifting input receiver circuit from high external voltage to low internal supply voltage
US6801080B1 (en) * 2003-04-07 2004-10-05 Pericom Semiconductor Corp. CMOS differential input buffer with source-follower input clamps
US7352229B1 (en) * 2006-07-10 2008-04-01 Altera Corporation Reference clock receiver compliant with LVPECL, LVDS and PCI-Express supporting both AC coupling and DC coupling
US7595660B2 (en) * 2007-08-16 2009-09-29 Texas Instruments Incorporated Low-delay complimentary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus
US11223359B2 (en) * 2016-03-31 2022-01-11 Qualcomm Incorporated Power efficient voltage level translator circuit
CN114430253B (zh) * 2022-01-27 2023-04-14 深圳市九天睿芯科技有限公司 一种信号放大电路

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4527078A (en) * 1982-08-23 1985-07-02 Signetics Corporation Signal translator with supply voltage compensation particularly for use as interface between current tree logic and transistor-transistor logic
JPS59219007A (ja) * 1983-05-27 1984-12-10 Hitachi Ltd Ｍｏｓ増幅回路
JPS61269525A (ja) * 1985-05-24 1986-11-28 Nec Corp 電流切換型論理回路
US4644194A (en) * 1985-06-24 1987-02-17 Motorola, Inc. ECL to TTL voltage level translator
GB2209104A (en) * 1987-08-26 1989-04-26 Philips Nv An amplifier load circuit and an amplifier including the load circuit
US4849659A (en) * 1987-12-15 1989-07-18 North American Philips Corporation, Signetics Division Emitter-coupled logic circuit with three-state capability
US4806799A (en) * 1988-02-26 1989-02-21 Motorola, Inc. ECL to CMOS translator
EP0353508B1 (de) * 1988-07-22 1994-09-21 Siemens Aktiengesellschaft ECL-CMOS-Wandler
JPH0777346B2 (ja) * 1988-12-28 1995-08-16 株式会社東芝 論理レベル変換回路
US4988898A (en) * 1989-05-15 1991-01-29 National Semiconductor Corporation High speed ECL/CML to TTL translator circuit
US5013941A (en) * 1989-08-17 1991-05-07 National Semiconductor Corporation TTL to ECL/CML translator circuit
US5216298A (en) * 1989-12-14 1993-06-01 Mitsubishi Denki Kabushiki Kaisha ECL input buffer for BiCMOS
US5059829A (en) * 1990-09-04 1991-10-22 Motorola, Inc. Logic level shifting circuit with minimal delay
US5068551A (en) * 1990-09-21 1991-11-26 National Semiconductor Corporation Apparatus and method for translating ECL signals to CMOS signals
US5148061A (en) * 1991-02-27 1992-09-15 Motorola, Inc. ECL to CMOS translation and latch logic circuit
US5148059A (en) * 1991-04-02 1992-09-15 International Business Machines Corporation CMOS and ECL logic circuit requiring no interface circuitry

Also Published As

Publication number Publication date
US5315179A (en) 1994-05-24
DE69315937D1 (de) 1998-02-05
JPH06204845A (ja) 1994-07-22
EP0794620A3 (en) 1997-10-29
DE69315937T2 (de) 1998-06-18
EP0794620A2 (en) 1997-09-10
EP0590247A3 (enExample) 1994-04-27
EP0590247A2 (en) 1994-04-06
EP0590247B1 (en) 1997-12-29

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19930922

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid