JPH06204845A - Bicmosレベル変換回路 - Google Patents
Bicmosレベル変換回路Info
- Publication number
- JPH06204845A JPH06204845A JP5259196A JP25919693A JPH06204845A JP H06204845 A JPH06204845 A JP H06204845A JP 5259196 A JP5259196 A JP 5259196A JP 25919693 A JP25919693 A JP 25919693A JP H06204845 A JPH06204845 A JP H06204845A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- emitter
- voltage level
- coupled
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 title claims description 11
- 239000000872 buffer Substances 0.000 claims abstract description 16
- 230000004044 response Effects 0.000 claims description 12
- 230000002829 reductive effect Effects 0.000 abstract description 9
- 229920006395 saturated elastomer Polymers 0.000 abstract description 3
- 238000004132 cross linking Methods 0.000 abstract 2
- 230000007704 transition Effects 0.000 abstract 1
- 230000001419 dependent effect Effects 0.000 description 16
- 230000036961 partial effect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 230000001105 regulatory effect Effects 0.000 description 4
- 230000002411 adverse Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000006880 cross-coupling reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
- H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
- H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]
- H03K19/017527—Interface arrangements using a combination of bipolar and field effect transistors [BIFET] with at least one differential stage
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US951,959 | 1992-09-28 | ||
| US07/951,959 US5315179A (en) | 1992-09-28 | 1992-09-28 | BICMOS level converter circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06204845A true JPH06204845A (ja) | 1994-07-22 |
Family
ID=25492392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5259196A Pending JPH06204845A (ja) | 1992-09-28 | 1993-09-22 | Bicmosレベル変換回路 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5315179A (enExample) |
| EP (2) | EP0794620A3 (enExample) |
| JP (1) | JPH06204845A (enExample) |
| KR (1) | KR940008261A (enExample) |
| DE (1) | DE69315937T2 (enExample) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1236879B (it) * | 1989-11-22 | 1993-04-26 | Sgs Thomson Microelectronics | Circuito elettronico comparatore |
| TW307064B (enExample) * | 1993-09-08 | 1997-06-01 | Advanced Micro Devices Inc | |
| US5485106A (en) * | 1994-04-05 | 1996-01-16 | Sun Microsystems, Inc. | ECL to CMOS converter |
| US5446400A (en) * | 1994-11-07 | 1995-08-29 | Motorola Inc. | GTL compatible BICMOS input stage |
| US5502405A (en) * | 1994-11-08 | 1996-03-26 | Cypress Semiconductor Corporation | Method and apparatus for CML/EC to CMOS/TTL translators |
| US5675809A (en) * | 1995-02-10 | 1997-10-07 | Ncr Corporation | Voltage control circuit for a dual voltage bus computer system |
| US6600338B1 (en) * | 2001-05-04 | 2003-07-29 | Rambus, Inc. | Apparatus and method for level-shifting input receiver circuit from high external voltage to low internal supply voltage |
| US6801080B1 (en) * | 2003-04-07 | 2004-10-05 | Pericom Semiconductor Corp. | CMOS differential input buffer with source-follower input clamps |
| US7352229B1 (en) * | 2006-07-10 | 2008-04-01 | Altera Corporation | Reference clock receiver compliant with LVPECL, LVDS and PCI-Express supporting both AC coupling and DC coupling |
| US7595660B2 (en) * | 2007-08-16 | 2009-09-29 | Texas Instruments Incorporated | Low-delay complimentary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus |
| US11223359B2 (en) * | 2016-03-31 | 2022-01-11 | Qualcomm Incorporated | Power efficient voltage level translator circuit |
| CN114430253B (zh) * | 2022-01-27 | 2023-04-14 | 深圳市九天睿芯科技有限公司 | 一种信号放大电路 |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4527078A (en) * | 1982-08-23 | 1985-07-02 | Signetics Corporation | Signal translator with supply voltage compensation particularly for use as interface between current tree logic and transistor-transistor logic |
| JPS59219007A (ja) * | 1983-05-27 | 1984-12-10 | Hitachi Ltd | Mos増幅回路 |
| JPS61269525A (ja) * | 1985-05-24 | 1986-11-28 | Nec Corp | 電流切換型論理回路 |
| US4644194A (en) * | 1985-06-24 | 1987-02-17 | Motorola, Inc. | ECL to TTL voltage level translator |
| GB2209104A (en) * | 1987-08-26 | 1989-04-26 | Philips Nv | An amplifier load circuit and an amplifier including the load circuit |
| US4849659A (en) * | 1987-12-15 | 1989-07-18 | North American Philips Corporation, Signetics Division | Emitter-coupled logic circuit with three-state capability |
| US4806799A (en) * | 1988-02-26 | 1989-02-21 | Motorola, Inc. | ECL to CMOS translator |
| DE58908391D1 (de) * | 1988-07-22 | 1994-10-27 | Siemens Ag | ECL-CMOS-Wandler. |
| JPH0777346B2 (ja) * | 1988-12-28 | 1995-08-16 | 株式会社東芝 | 論理レベル変換回路 |
| US4988898A (en) * | 1989-05-15 | 1991-01-29 | National Semiconductor Corporation | High speed ECL/CML to TTL translator circuit |
| US5013941A (en) * | 1989-08-17 | 1991-05-07 | National Semiconductor Corporation | TTL to ECL/CML translator circuit |
| US5216298A (en) * | 1989-12-14 | 1993-06-01 | Mitsubishi Denki Kabushiki Kaisha | ECL input buffer for BiCMOS |
| US5059829A (en) * | 1990-09-04 | 1991-10-22 | Motorola, Inc. | Logic level shifting circuit with minimal delay |
| US5068551A (en) * | 1990-09-21 | 1991-11-26 | National Semiconductor Corporation | Apparatus and method for translating ECL signals to CMOS signals |
| US5148061A (en) * | 1991-02-27 | 1992-09-15 | Motorola, Inc. | ECL to CMOS translation and latch logic circuit |
| US5148059A (en) * | 1991-04-02 | 1992-09-15 | International Business Machines Corporation | CMOS and ECL logic circuit requiring no interface circuitry |
-
1992
- 1992-09-28 US US07/951,959 patent/US5315179A/en not_active Expired - Fee Related
-
1993
- 1993-07-02 DE DE69315937T patent/DE69315937T2/de not_active Expired - Fee Related
- 1993-07-02 EP EP97108906A patent/EP0794620A3/en not_active Withdrawn
- 1993-07-02 EP EP93110587A patent/EP0590247B1/en not_active Expired - Lifetime
- 1993-09-22 JP JP5259196A patent/JPH06204845A/ja active Pending
- 1993-09-22 KR KR1019930019279A patent/KR940008261A/ko not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| EP0794620A3 (en) | 1997-10-29 |
| EP0590247A3 (enExample) | 1994-04-27 |
| EP0794620A2 (en) | 1997-09-10 |
| EP0590247A2 (en) | 1994-04-06 |
| KR940008261A (ko) | 1994-04-29 |
| US5315179A (en) | 1994-05-24 |
| DE69315937T2 (de) | 1998-06-18 |
| DE69315937D1 (de) | 1998-02-05 |
| EP0590247B1 (en) | 1997-12-29 |
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