KR940001446A - 반도체 소자의 게이트 산화막 형성방법 - Google Patents
반도체 소자의 게이트 산화막 형성방법 Download PDFInfo
- Publication number
- KR940001446A KR940001446A KR1019920010209A KR920010209A KR940001446A KR 940001446 A KR940001446 A KR 940001446A KR 1019920010209 A KR1019920010209 A KR 1019920010209A KR 920010209 A KR920010209 A KR 920010209A KR 940001446 A KR940001446 A KR 940001446A
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- gate oxide
- semiconductor device
- gas
- diffusion furnace
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 title claims abstract 8
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000009792 diffusion process Methods 0.000 claims 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims 2
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Formation Of Insulating Films (AREA)
Abstract
본 발명은 반도체 소자의 게이트 산화막 헝성방법에 관한 것으로, 반도체 소자외 제조공정중 게이트 산화막 형성공정시 LPCVD 확산로내에서 CVD 게 이트 산화막을 증착한후 인-시튜 0 어닐링을 실시하여 상기 CVD 게이트 산화막 하부면과 실리콘 기판 상부면 사이에 열적게이트 산화막을 성장시켜 CVD 게이트 산화막/열적 게이트 산화막으로 이루어진 게이트 산화막을 형성하는 기술에 관하여 기술되어 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 의하여 반도체 기판상에 게이트 산화막을 형성한 상태의 단면도.
Claims (3)
- 반도체 소자의 게이트 산화막 형성방법에 있어서, 반도체 기판상에 필드산화막이 형성된 웨이퍼를 LPCVD확산로에 넣는 단계와, 상기 LPCVD확산로 내부 압력을 진공펌프를 이용하여 예정된 압력까지 낮추는 단계와, 상기 확산로내의 조건을 예정된 온도 및 압력으로 하여 예정된 양의 O2개스와 TEOS 개스를 주입하여 상기 반도체 기판상부에 CVD 게이트 산화막을 증착하는 단계와, N2개스를 상기 확산로내부로 주입하여 확산로내부틀 정화시킨다음. 확산로내의 조건을 예정된 온도까지 상승시킨후, 예정된 양의 O2개스를 주입하여 상기 반도체 기판과 상기 CVD 게이트 산화막과의 접합면에 열적 게이트 산화막을 성장시 켜 CVD 게 이트 산화막/열 적 게 이트 산화막으로 이루어진 게이트 산화막을 형성하는 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성방법.
- 제1항에 있어서, 상기 CVD게이트산화막을 증착하는 단계에서, 상기 확산로내의 온도는710±10'C, 압력은 30-6OPa로 하고 상기 02개스는 10cc/min, TEOS 개스를 70-97cc/min 만큼 주입하는 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성방법.
- 제 1항에 있어서, 상기 열적 게이트 산화막을 성 장하는 단계에서, 상기 확산로내의 온도는 850± 10℃로 하고 상기 02개스는 1.000cc/min만큼 주입하는 것을 특징으로 하는 반도체 소자의 게이트 산화막 헝성방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920010209A KR100220298B1 (ko) | 1992-06-12 | 1992-06-12 | 반도체 소자의 게이트 산화막 형성방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920010209A KR100220298B1 (ko) | 1992-06-12 | 1992-06-12 | 반도체 소자의 게이트 산화막 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940001446A true KR940001446A (ko) | 1994-01-11 |
KR100220298B1 KR100220298B1 (ko) | 1999-09-15 |
Family
ID=19334585
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920010209A KR100220298B1 (ko) | 1992-06-12 | 1992-06-12 | 반도체 소자의 게이트 산화막 형성방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100220298B1 (ko) |
-
1992
- 1992-06-12 KR KR1019920010209A patent/KR100220298B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100220298B1 (ko) | 1999-09-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR880005666A (ko) | 선택적으로 산화된 실리콘 기판상에 에피택셜 실리콘 층과 다결정 실리콘 층을 동시에 성장시키는 증착방법 | |
CN1284743A (zh) | 制造半导体器件中的晶体管的方法 | |
KR920010829A (ko) | 반도체장치의 필드산화막 형성방법 | |
KR890001190A (ko) | 반도체 기억소자 및 제조방법 | |
KR940001446A (ko) | 반도체 소자의 게이트 산화막 형성방법 | |
KR870002666A (ko) | 반도체장치의 제조방법 | |
JP2715734B2 (ja) | Soiの形成方法 | |
KR100305201B1 (ko) | 반도체소자의게이트절연막형성방법 | |
KR950030336A (ko) | 캐패시터의 유전체막 형성방법 | |
KR940001392A (ko) | 반도체 소자의 캐패시터 유전체 형성방법 | |
KR920005359A (ko) | 반도체 소자의 소자격리방법 | |
KR970053455A (ko) | 샐로우 트렌치 소자분리방법 | |
KR970003470A (ko) | 실리콘 전극의 제조 방법 | |
JPS54162477A (en) | Lateral transistor | |
JPS5773930A (en) | Forming method for polycrystalline silicon film with addition of impurities for diffusion source | |
KR950021264A (ko) | 저온 게이트 산화막의 제조방법 | |
JPS5567168A (en) | Preparation of insulating gate type field-effect transistor | |
KR970030278A (ko) | 저압화학기상증착법에 의한 에피택셜 실로콘층 형성방법 | |
KR19990006066A (ko) | 반도체 소자의 웰 형성방법 | |
KR970003790A (ko) | 반도체 소자 분리방법 | |
KR970052791A (ko) | 반도체 소자의 필드 산화막 형성 방법 | |
JPS6430259A (en) | Semiconductor device | |
JPS5721814A (en) | Manufacture of semiconductor device | |
KR940001346A (ko) | 반도체 소자분리막 제조방법 | |
KR920018969A (ko) | 바이폴라 트랜지스터의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20090526 Year of fee payment: 11 |
|
LAPS | Lapse due to unpaid annual fee |