KR930017174A - Capacitor Manufacturing Method - Google Patents

Capacitor Manufacturing Method Download PDF

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Publication number
KR930017174A
KR930017174A KR1019920000477A KR920000477A KR930017174A KR 930017174 A KR930017174 A KR 930017174A KR 1019920000477 A KR1019920000477 A KR 1019920000477A KR 920000477 A KR920000477 A KR 920000477A KR 930017174 A KR930017174 A KR 930017174A
Authority
KR
South Korea
Prior art keywords
silicon substrate
exposure
rotating
storage node
manufacturing
Prior art date
Application number
KR1019920000477A
Other languages
Korean (ko)
Other versions
KR950013383B1 (en
Inventor
전영권
윤광현
Original Assignee
문정관
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정관, 금성일렉트론 주식회사 filed Critical 문정관
Priority to KR1019920000477A priority Critical patent/KR950013383B1/en
Priority to TW081108806A priority patent/TW221720B/zh
Priority to JP32629592A priority patent/JP3359945B2/en
Priority to DE4238404A priority patent/DE4238404B4/en
Priority to US07/975,884 priority patent/US5336630A/en
Publication of KR930017174A publication Critical patent/KR930017174A/en
Application granted granted Critical
Publication of KR950013383B1 publication Critical patent/KR950013383B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

반도체 소자의 제조방법에서 스토리지 노드, 유전체막 및 플레이트 모드를 포함하는 커패시터 제조공정에서, 스토리지노드의 커패시턴스를 극대화시키기 위해 이중 노광법으로 실리콘 기판은 바둑판모양과 같이 고립되거나 직교하는 모양으로 패터닝한다.In a capacitor manufacturing process including a storage node, a dielectric film, and a plate mode in a method of manufacturing a semiconductor device, a silicon substrate is patterned in an isolated or orthogonal shape, such as a checkerboard, by a double exposure method in order to maximize the capacitance of the storage node.

따라서, 본 발명에 따라 스토리지 노드의 커패시턴스가 극대화된다.Thus, the capacitance of the storage node is maximized in accordance with the present invention.

Description

커패시처 제조방법Capacitor Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 2도는 본 발명에 따른 스토리지 노드 패턴 공정단면도.2 is a cross-sectional view of a storage node pattern process according to the present invention.

Claims (2)

실리콘 기판상에 포지티브 또는 네거티브 감광막을 형성시킨 후 다수의 평행한 미세선을 전사하는 마스크를 이용하여 1차 노광을 실시하는 공정과, 상기 감광막이 형성된 실리콘 기판을 90°회전시켜 2차 노광을 실시하는 공정과, 상기 감광막을 현상하여, 상기 1차 및 2차 노광에 따른 형상과 같은 모양을 유지하도록 상기 실리콘 기판을 소정깊이까지 식각시키는 공정과, 상기 식각된 실리콘기판의 전표면에 유체막과 플레이트 노드를 차례로 형성시키는 공정을 순차적으로 실시함을 특징으로 하는 커패시터 제조방법.After forming a positive or negative photoresist film on the silicon substrate, the first exposure using a mask for transferring a plurality of parallel fine lines, and the second exposure by rotating the silicon substrate on which the photosensitive film is formed by 90 ° And etching the silicon substrate to a predetermined depth so that the photosensitive film is developed to maintain a shape identical to the shape of the first and second exposures, and a fluid film is formed on the entire surface of the etched silicon substrate. Capacitor manufacturing method characterized in that the step of sequentially forming the plate node to perform sequentially. 제 1항에 있어서, 2차 노광시 실리콘 기판을 90°회전시키지 않고 마스크를 90°회전시켜 노광을 실시함을 특징으로 하는 커패시터 제조방법.The method of manufacturing a capacitor according to claim 1, wherein the exposure is performed by rotating the mask by 90 degrees without rotating the silicon substrate by 90 degrees during the second exposure. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019920000477A 1991-11-15 1992-01-15 Capacitor manufacturing process KR950013383B1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019920000477A KR950013383B1 (en) 1992-01-15 1992-01-15 Capacitor manufacturing process
TW081108806A TW221720B (en) 1991-11-15 1992-11-04
JP32629592A JP3359945B2 (en) 1991-11-15 1992-11-12 Method for manufacturing semiconductor memory device
DE4238404A DE4238404B4 (en) 1991-11-15 1992-11-13 Method for producing a semiconductor memory device
US07/975,884 US5336630A (en) 1991-11-15 1992-11-13 Method of making semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920000477A KR950013383B1 (en) 1992-01-15 1992-01-15 Capacitor manufacturing process

Publications (2)

Publication Number Publication Date
KR930017174A true KR930017174A (en) 1993-08-30
KR950013383B1 KR950013383B1 (en) 1995-11-02

Family

ID=19327888

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920000477A KR950013383B1 (en) 1991-11-15 1992-01-15 Capacitor manufacturing process

Country Status (1)

Country Link
KR (1) KR950013383B1 (en)

Also Published As

Publication number Publication date
KR950013383B1 (en) 1995-11-02

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