KR950007111A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR950007111A
KR950007111A KR1019930016157A KR930016157A KR950007111A KR 950007111 A KR950007111 A KR 950007111A KR 1019930016157 A KR1019930016157 A KR 1019930016157A KR 930016157 A KR930016157 A KR 930016157A KR 950007111 A KR950007111 A KR 950007111A
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KR
South Korea
Prior art keywords
capacitor
pattern
polysilicon layer
forming
manufacturing
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KR1019930016157A
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Korean (ko)
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KR970000225B1 (en
Inventor
김명선
김준모
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김주용
현대전자산업 주식회사
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Priority to KR1019930016157A priority Critical patent/KR970000225B1/en
Publication of KR950007111A publication Critical patent/KR950007111A/en
Application granted granted Critical
Publication of KR970000225B1 publication Critical patent/KR970000225B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 장치의 캐패시터 제조 방법에 관한 것으로서, 기판과의 접촉을 위한 접촉공이 형성되어 있는 층간절연막상에 폴리 실리콘층을 형성한 후, 상측에 홈을 갖는 감광막 패턴을 이중 노광에 의해 형성하고, 상기 감광막 패턴의 표면을 실리레이션한 다음 실리레이션막의 상측 일부를 이방성식각 방법으로 제거하고 반응성 이온 에칭 방법으로 이중틀체 형상의 실리레이션막 패턴을 한정하여, 이를 마스크로 폴리 실리콘층을 소정 두께 식각하여 저면이 상기 접촉공을 메운 폴리 실리콘층과 연결되는 이중틀체 형상의 캐패시터를 형성한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, wherein a polysilicon layer is formed on an interlayer insulating film in which contact holes for contact with a substrate are formed, and then a photosensitive film pattern having a groove on the upper side thereof is formed by double exposure. After silencing the surface of the photoresist layer pattern, the upper part of the silicide layer is removed by anisotropic etching, and a reactive silicon layer is used to define a double-layered silicide layer pattern. As a result, a double-shaped capacitor having a bottom surface connected to the polysilicon layer filling the contact hole is formed.

따라서, 제조공정이 간단하여 캐패시터의 제조가 용이하고, 폴리 실리콘층의 표면이 여러번 식각되지 않으므로 캐패시터 표면의 결함이 감소하며, 캐패시터의 측벽이 균일한 높이를 유지하므로 캐패시터의 정전용량이 증가되어 반도체 장치의 신뢰성이 증가된다.Therefore, the manufacturing process is simple, so that the manufacturing of the capacitor is easy, the surface of the polysilicon layer is not etched many times, so the defects on the surface of the capacitor are reduced, and the capacitance of the capacitor is increased because the sidewall of the capacitor maintains a uniform height, thereby increasing the semiconductor capacity. The reliability of the device is increased.

Description

반도체 장치의 캐패시터 제조 방법Capacitor Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도 (A)~(E)는 본 발명에 따른 반도체 장치의 캐패시터 제조 공정도,2 (A) to (E) is a manufacturing process diagram of a capacitor of a semiconductor device according to the present invention,

제3도는 본 발명에 따른 반도체 장치의 캐패시터 일실시예의 사시도.3 is a perspective view of one embodiment of a capacitor of a semiconductor device according to the present invention.

Claims (3)

반도체 장치의 제조 방법에 있어서, 반도체 기판상에 평탄화를 위한 층간 절연막을 형성하는 단계와, 상기 반도체 기판의 캐패시터와 접촉될 예정 영역상의 층간 절연막을 제거하여 반도체 기판을 노출시키는 접촉공을 형성하는 단계와, 상기 층간 절연막상에 폴리 실리콘층을 형성하여 상기 접촉공을 메우는 단계와, 상기 접촉공상의 폴리 실리콘을 보호하는 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴의 상측 일부를 제거하여 홈을 형성하는 단계와, 상기 감광막 패턴과 홈의 표면에 실리레이션막을 형성하는 단계와, 상기 실리레이션막을 마스크로하여 노출되어 있는 폴리 실리콘층을 제거하여 층간절연막을 노출시키는 폴리 실리콘층 패턴을 형성하는 단계와, 상기 구조의 실리레이션막을 전면 이방성 식각하여 이중 틀체 형상의 실리레이션막 패턴을 형성하는 단계와, 상기 실리레이션막 패턴을 마스크로하여 폴리실리콘층 패턴을 소정의 두께 만큼 제거하여 상기 접촉공을 메운 폴리 실리콘층과 저면이 연결되는 이중틀체 형상의 캐패시터를 형성하고 상기 실리레이션 패턴을 제거하는 단계를 포함하는 반도체 장치의 캐패시터 제조 방법.A method of manufacturing a semiconductor device, comprising: forming an interlayer insulating film for planarization on a semiconductor substrate, and forming a contact hole for exposing the semiconductor substrate by removing the interlayer insulating film on a predetermined region to be in contact with a capacitor of the semiconductor substrate; Forming a polysilicon layer on the interlayer insulating film to fill the contact hole, forming a photoresist pattern protecting the polysilicon of the contact hole, and removing a portion of an upper side of the photoresist pattern to form a groove. Forming a silicide film on the surface of the photoresist pattern and the groove, removing the exposed polysilicon layer using the silicide film as a mask, and forming a polysilicon layer pattern exposing the interlayer insulating film; Double silencing the silicide layer having the structure Forming a film pattern, and removing the polysilicon layer pattern by a predetermined thickness using the silicide film pattern as a mask to form a double-shaped capacitor in which a bottom surface is connected to the polysilicon layer filling the contact hole; A method for manufacturing a capacitor of a semiconductor device comprising the step of removing the sillation pattern. 제1항에 있어서, 상기 감광막 패턴을 비노광 부분이 패턴이 되는 포지티브 감광액으로 형성하는 것을 특징으로 하는 반도체 장치의 캐패시터 제조 방법.The method of manufacturing a capacitor of a semiconductor device according to claim 1, wherein the photosensitive film pattern is formed of a positive photosensitive liquid in which a non-exposed portion becomes a pattern. 제1항에 있어서, 상기 폴리 실리콘층 패턴 형성공정과, 실리레이션막 패턴 형성 공정의 사이에 별도로 상기 실리레이션막의 상부를 소정두께 제거하여 감광막 패턴을 노출시키는 공정을 구비하는 것을 특징으로 하는 반도체 장치의 캐패시터 제조 방법.The semiconductor device according to claim 1, further comprising a step of exposing a photoresist pattern by removing a predetermined thickness of the upper part of the silicide film separately between the polysilicon layer pattern forming step and the silicide film pattern forming step. Capacitor manufacturing method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930016157A 1993-08-19 1993-08-19 Method for manufacturing a semiconductor capacitor KR970000225B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930016157A KR970000225B1 (en) 1993-08-19 1993-08-19 Method for manufacturing a semiconductor capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930016157A KR970000225B1 (en) 1993-08-19 1993-08-19 Method for manufacturing a semiconductor capacitor

Publications (2)

Publication Number Publication Date
KR950007111A true KR950007111A (en) 1995-03-21
KR970000225B1 KR970000225B1 (en) 1997-01-06

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KR1019930016157A KR970000225B1 (en) 1993-08-19 1993-08-19 Method for manufacturing a semiconductor capacitor

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100246649B1 (en) * 1995-05-31 2000-03-15 가네꼬 히사시 Method for forming a capacitor in a memory cell in a dram

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100246649B1 (en) * 1995-05-31 2000-03-15 가네꼬 히사시 Method for forming a capacitor in a memory cell in a dram

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Publication number Publication date
KR970000225B1 (en) 1997-01-06

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