KR960026852A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

Info

Publication number
KR960026852A
KR960026852A KR1019940039028A KR19940039028A KR960026852A KR 960026852 A KR960026852 A KR 960026852A KR 1019940039028 A KR1019940039028 A KR 1019940039028A KR 19940039028 A KR19940039028 A KR 19940039028A KR 960026852 A KR960026852 A KR 960026852A
Authority
KR
South Korea
Prior art keywords
conductive layer
insulating layer
forming
mask
spacer
Prior art date
Application number
KR1019940039028A
Other languages
Korean (ko)
Inventor
이병렬
유의규
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940039028A priority Critical patent/KR960026852A/en
Publication of KR960026852A publication Critical patent/KR960026852A/en

Links

Abstract

본 발명은 반도체소자의 캐패시터 제조방법에 관한 것으로, 반도체 기판 상부에 하부절연층과 제1절연막 및 제2절연막을 순차적으로 형성하고 그 상부에 콘택마스크보다 큰 마스크를 이용하여 상기 제2절연막을 식각한 다음, 상기 제2절연막의 측벽에 제1도전층 스페이서를 형성하고 상기 제2절연막을 제거한 다음, 상기 제1도전층 스페이서를 마스크로 하여 상기 반도체기판을 노출시키는 콘택홀을 형성하고 상기 반도체기판의 예정된 부분에 접속되는 제2도전층을 일정두께 형성한 다음, 저장전극마스크를 이용하여 상기 제2도전층을 식각하고 상기 제2도전층에 연결된 제3도전층 스페이서를 형성함으로써 표면적이 증가된 저장전극을 형성하고 후공정에서 충분한 정전용량을 확보할 수 있는 캐패시터를 형성함으로써 반도체소자의 고집적화를 가능하게 하고 이에 따른 반도체소자의 신뢰성을 향상시키는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, wherein a lower insulating layer, a first insulating layer, and a second insulating layer are sequentially formed on an upper surface of a semiconductor substrate, and the second insulating layer is etched using a mask larger than a contact mask thereon. Next, a first conductive layer spacer is formed on sidewalls of the second insulating layer, the second insulating layer is removed, and then a contact hole for exposing the semiconductor substrate is formed using the first conductive layer spacer as a mask. After forming a second conductive layer connected to a predetermined portion of the predetermined thickness, the surface area is increased by etching the second conductive layer using a storage electrode mask and forming a third conductive layer spacer connected to the second conductive layer. High integration of semiconductor devices is possible by forming storage electrodes and capacitors that can ensure sufficient capacitance in later processes. A technique to it and thereby improve the reliability of the semiconductor device according.

Description

반도체소자의 캐패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명의 실시예에 따른 반도체소자의 캐패시터 제조공정을 도시한 단면도.2A to 2D are sectional views showing a capacitor manufacturing process of a semiconductor device according to an embodiment of the present invention.

Claims (8)

반도체기판 상부에 하부절연층과 제1절연막을 순차적으로 형성하는 공정과, 상기 제1절연막 상부에 제2절연막을 형성하는 공정과, 상기 제2절연막 상부에 제1감광막패턴을 형성하는 공정과, 상기 제1감광막패턴을 이용하여 상기 제2절연막을 식각하는 공정과, 상기 제1감광막패턴을 제거하는 공정과, 상기 제2절연막 측벽에 제1도전층 스페이서를 형성하는 공정과, 상기제2절연막을 제거하는 공정과, 상기 제1도전층 스페이서와 제1절연막을 마스크로 하여 상기 하부절연층을 식각하여 콘택홀을 형성하는 공정과, 상기 콘택홀을 통하여 상기 반도체기판에 접속되는 제2도전층을 형성하는 공정과, 상기 제2도전층 상부에 제2감광막패턴을 형성하는 공정과, 상기 제2감광막패턴을 마스크로하여 상기 제2도전층을 식각하는 공정과, 상기 제2도전층과 제2감광막패턴 측벽에 제3도전층 스페이서를 형성하는 공정과, 상기 제2감광막패턴을 제거함으로써 표면적이 증가된 저장전극을 형성하는 반도체소자의 캐패시터 제조방법.Sequentially forming a lower insulating layer and a first insulating film on the semiconductor substrate, forming a second insulating film on the first insulating film, forming a first photoresist film pattern on the second insulating film, Etching the second insulating layer using the first photoresist pattern, removing the first photoresist pattern, forming a first conductive layer spacer on the sidewall of the second insulating layer, and forming the second insulating layer Forming a contact hole by etching the lower insulating layer using the first conductive layer spacer and the first insulating layer as a mask, and a second conductive layer connected to the semiconductor substrate through the contact hole. Forming a second photosensitive film pattern on the second conductive layer, etching the second conductive layer using the second photosensitive film pattern as a mask, and forming the second conductive layer and the second conductive layer 2 dimming The step of forming the third conductive layer patterns on the side wall spacer and the capacitor manufacturing method of the semiconductor device which forms the second of the surface area by removing the second photosensitive film pattern increases storage electrode. 제1항에 있어서, 상기 제1절연막은 상기 제2절연막과 일정한 식각선택비 차이를 갖는 물질로 형성되는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the first insulating layer is formed of a material having a predetermined difference in etching selectivity from the second insulating layer. 제1항에 있어서, 상기 예정된 부분은 불순물 확산영역인 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the predetermined portion is an impurity diffusion region. 제1항에 있어서, 상기 제1,2,3도전층은 다결정실리콘막으로 형성되는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the first, second and third conductive layers are formed of a polycrystalline silicon film. 제1항에 있어서, 상기 제1감광막패턴은 콘택마스크보다 크게 형성되는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the first photoresist pattern is larger than a contact mask. 제1항에 있어서, 상기 콘택홀은 상기 제1도전층 스페이서의 두께로서 조절되는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the contact hole is adjusted as a thickness of the first conductive layer spacer. 제1항에 있어서, 상기 제2감광막패턴은 저장전극마스크를 이용한 식각공정으로 형성되는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the second photoresist pattern is formed by an etching process using a storage electrode mask. 제1항에 있어서, 상기 제2절연막 제거공정은 상기 제1도전층 스페이서 및 제1절연막과의 식각선택비 차이를 이용한 습식방법으로 제거되는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The method of claim 1, wherein the removing of the second insulating layer is performed by a wet method using a difference in etching selectivity between the first conductive layer spacer and the first insulating layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940039028A 1994-12-29 1994-12-29 Capacitor Manufacturing Method of Semiconductor Device KR960026852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940039028A KR960026852A (en) 1994-12-29 1994-12-29 Capacitor Manufacturing Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940039028A KR960026852A (en) 1994-12-29 1994-12-29 Capacitor Manufacturing Method of Semiconductor Device

Publications (1)

Publication Number Publication Date
KR960026852A true KR960026852A (en) 1996-07-22

Family

ID=66647484

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940039028A KR960026852A (en) 1994-12-29 1994-12-29 Capacitor Manufacturing Method of Semiconductor Device

Country Status (1)

Country Link
KR (1) KR960026852A (en)

Similar Documents

Publication Publication Date Title
KR960006030A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960026852A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960026793A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960026804A (en) Stack capacitor manufacturing method of semiconductor device
KR960026795A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970054008A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960026818A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960026791A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960026811A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960026856A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960026870A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960032747A (en) Capacitor Formation Method of Semiconductor Device
KR960026812A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960026164A (en) Method for manufacturing storage electrode of semiconductor device
KR960026819A (en) Method for manufacturing storage electrode of semiconductor device
KR960026854A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960026857A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960026835A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970024133A (en) Method for forming storage electrode of semiconductor device
KR960026813A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960026850A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970018496A (en) Method for forming storage electrode of semiconductor device
KR960026864A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970003991A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970053940A (en) Method for forming storage electrode of semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination