KR950025980A - Method of manufacturing semiconductor memory device - Google Patents

Method of manufacturing semiconductor memory device Download PDF

Info

Publication number
KR950025980A
KR950025980A KR1019940002283A KR19940002283A KR950025980A KR 950025980 A KR950025980 A KR 950025980A KR 1019940002283 A KR1019940002283 A KR 1019940002283A KR 19940002283 A KR19940002283 A KR 19940002283A KR 950025980 A KR950025980 A KR 950025980A
Authority
KR
South Korea
Prior art keywords
polysilicon film
semiconductor memory
memory device
forming
cell
Prior art date
Application number
KR1019940002283A
Other languages
Korean (ko)
Other versions
KR970010772B1 (en
Inventor
최양규
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940002283A priority Critical patent/KR970010772B1/en
Publication of KR950025980A publication Critical patent/KR950025980A/en
Application granted granted Critical
Publication of KR970010772B1 publication Critical patent/KR970010772B1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 DRAM 소자의 캐패시터 형성시 셀 경계 부위에 캐패시터 역할을 하지 못하는 여분의 캐패시터를 만들어서, 이 여분의 캐패시터를 경사식각하여 웨이피의 전체적인 토포로지를 완화시키는 것으로 이후에 금속층을 도포했을 경우 최대 경사 각도를 갖는 점에서 금속층의 수직 두께를 낮추어, 금속층 식각 시간을 줄일 수 있으며, 금속층 식각 시간이 줄면, 금속 배선 감광막의 두께를 낮추어도 되고, 낮추어진 감광막 두께는 금속배선 사진 공정시 분해능(Resolution) 향상과 도프마진(DOF : Depth of Focus Margin)을 가져오는 효과가 있다.According to the present invention, an extra capacitor that does not function as a capacitor at a cell boundary when forming a capacitor of a semiconductor DRAM device is made, and the extra capacitor is inclined to alleviate the overall topology of the wafer. By reducing the vertical thickness of the metal layer at the inclination angle, the etching time of the metal layer can be reduced, and when the etching time of the metal layer is reduced, the thickness of the metal wiring photoresist film may be lowered. ) And improves Depth of Focus Margin (DOF).

Description

반도체 기억소자 제조 방법Method of manufacturing semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 제조 방법에 따라 형성된 셀과 주변회로 경계부의 단면도,1 is a cross-sectional view of a cell and a peripheral circuit boundary formed according to a conventional manufacturing method,

제2A도 내지 제2D도는 본 발명에 따른 셀과 주변회로 경계부의 제조 공정도.2A to 2D are manufacturing process diagrams of the cell and peripheral circuit boundary portion according to the present invention.

Claims (3)

반도체 기억소자의 셀과 주변회로와의 경계부위 토포로지를 완화시키는 반도체 기억소자 제조 방법에 있어서 ; 셀내의 예정된 부위에 콘택홀을 형성하고 전하 저장전극용 폴리실리콘막을 적층하는 단계; 리소그래피 공정으로 폴리실리콘막 패턴을 형성하여 전하저장전극(5)을 디파인(define)하되 셀과 주변회로 경계 부위에도 여분의 폴리실리콘막 패턴(5')을 형성하는 단계 ; 상기 패턴닝된 폴리실리콘막(5, 5')의 노출된 표면에 유전막(6)을 형성하고 상기 유전막(6)상에 플레이트 전극용 폴리실리콘막(7)을 형성하는 단계 ; 포토리소그래피 공정으로 상기 플레이트 전극용 폴리실리콘막(7)상의 셀 영역에만 감광막(8)을 형성하는 단계 ; 상기 감광막(8)을 식각장벽만으로 사용하여 플레이트 전극용 폴리실리콘막(7), 유전막(6), 여분의 폴리실리콘막 패턴(5')을 차례로 식각하되 식각부위가 완만한 경사를 가지도록 식각하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 기억소자 제조방법.A semiconductor memory device manufacturing method for relaxing a boundary topology between a cell and a peripheral circuit of a semiconductor memory device; Forming a contact hole in a predetermined portion of the cell and stacking a polysilicon film for a charge storage electrode; Forming a polysilicon film pattern by a lithography process to define the charge storage electrode 5, and to form an extra polysilicon film pattern 5 ′ at the boundary between the cell and the peripheral circuit; Forming a dielectric film (6) on the exposed surface of the patterned polysilicon film (5, 5 ') and forming a polysilicon film (7) for plate electrodes on the dielectric film (6); Forming a photosensitive film (8) only in the cell region on the polysilicon film (7) for the plate electrode by a photolithography process; Using the photoresist film 8 as an etch barrier only, the polysilicon film 7 for the plate electrode 7, the dielectric film 6, and the extra polysilicon film pattern 5 ′ are sequentially etched so that the etching portion has a gentle slope. A method of manufacturing a semiconductor memory device, characterized in that it comprises a step of. 제1항에 있어서, 상기 셀과 주변회로 경계 부위에 형성되는 여분의 폴리실리콘막 패턴(5')의 들뜸을 방지하기 위하여 이 폴리실리콘막 패턴(5')을 콘택시키는 것을 특징으로 하는 반도체 기억소자 제조 방법.The semiconductor memory according to claim 1, wherein the polysilicon film pattern 5 'is contacted in order to prevent the extra polysilicon film pattern 5' formed at the boundary between the cell and the peripheral circuit. Device manufacturing method. 제1항에 있어서, 상기 플레이트 전극용 폴리실리콘막(7), 유전막(6), 여분의 폴리실리콘막 패턴(5')의 식각은 물리적인 식각수단으로 경사식각하는 것을 특징으로 하는 반도체 기억소자 제조 방법.2. The semiconductor memory device according to claim 1, wherein etching of the polysilicon film (7), the dielectric film (6), and the extra polysilicon film pattern (5 ') for the plate electrode is obliquely etched by physical etching means. Manufacturing method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940002283A 1994-02-07 1994-02-07 Method for fabricating semiconductor memory KR970010772B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940002283A KR970010772B1 (en) 1994-02-07 1994-02-07 Method for fabricating semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940002283A KR970010772B1 (en) 1994-02-07 1994-02-07 Method for fabricating semiconductor memory

Publications (2)

Publication Number Publication Date
KR950025980A true KR950025980A (en) 1995-09-18
KR970010772B1 KR970010772B1 (en) 1997-06-30

Family

ID=19376949

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940002283A KR970010772B1 (en) 1994-02-07 1994-02-07 Method for fabricating semiconductor memory

Country Status (1)

Country Link
KR (1) KR970010772B1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980057121A (en) * 1996-12-30 1998-09-25 김영환 Manufacturing Method of Semiconductor Device
KR100234382B1 (en) * 1996-07-23 1999-12-15 윤종용 Planization method of semiconductor memory device
KR100301038B1 (en) * 1998-03-02 2001-09-06 윤종용 Semiconductor memory device containing COB and method of forming the same
KR100419748B1 (en) * 1996-09-06 2004-06-04 주식회사 하이닉스반도체 Method for fabricating semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100234382B1 (en) * 1996-07-23 1999-12-15 윤종용 Planization method of semiconductor memory device
KR100419748B1 (en) * 1996-09-06 2004-06-04 주식회사 하이닉스반도체 Method for fabricating semiconductor device
KR19980057121A (en) * 1996-12-30 1998-09-25 김영환 Manufacturing Method of Semiconductor Device
KR100301038B1 (en) * 1998-03-02 2001-09-06 윤종용 Semiconductor memory device containing COB and method of forming the same

Also Published As

Publication number Publication date
KR970010772B1 (en) 1997-06-30

Similar Documents

Publication Publication Date Title
KR930015010A (en) Method for manufacturing charge storage electrode of semiconductor memory device
KR100255064B1 (en) Method of forming a capacitor over a semiconductor substrate
KR950004516A (en) Manufacturing Method of Semiconductor Memory Device
KR950025980A (en) Method of manufacturing semiconductor memory device
KR950007098A (en) DRAM cell manufacturing method
KR100369484B1 (en) Method for manufacturing capacitor of semiconductor device
KR950007168A (en) Method for manufacturing capacitor electrode of semiconductor device
KR930015004A (en) Method for forming charge storage electrode in DRAM cell
KR100419748B1 (en) Method for fabricating semiconductor device
KR950007111A (en) Capacitor Manufacturing Method of Semiconductor Device
KR940027165A (en) Method for Forming Stacked Capacitor of Semiconductor Device
KR940016766A (en) Capacitor Manufacturing Method of Semiconductor Device
KR19980055974A (en) Method of forming charge storage electrode of capacitor
KR19990016146A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970054008A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970003959A (en) Method of forming charge storage electrode of capacitor
KR950034782A (en) Capacitor Manufacturing Method of Semiconductor Device
KR950034730A (en) Capacitor Manufacturing Method in Semiconductor Memory Device
KR950010076A (en) DRAM cell manufacturing method of semiconductor device
KR980006321A (en) Capacitor Formation Method for DRAM Device
KR980012483A (en) Method for manufacturing semiconductor memory device
KR950002034A (en) Method for Forming Capacitor with Polyphase Structure Electrode
KR930003346A (en) Contact manufacturing method for high density devices
KR19990018061A (en) Rectangular capacitor storage node and manufacturing method
KR970013348A (en) Capacitor Manufacturing Method of Semiconductor Device

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100920

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee