KR930014931A - Semiconductor leadframe - Google Patents

Semiconductor leadframe Download PDF

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Publication number
KR930014931A
KR930014931A KR1019910022196A KR910022196A KR930014931A KR 930014931 A KR930014931 A KR 930014931A KR 1019910022196 A KR1019910022196 A KR 1019910022196A KR 910022196 A KR910022196 A KR 910022196A KR 930014931 A KR930014931 A KR 930014931A
Authority
KR
South Korea
Prior art keywords
lead frame
package
pad
semiconductor
holes
Prior art date
Application number
KR1019910022196A
Other languages
Korean (ko)
Other versions
KR940010548B1 (en
Inventor
권오식
정현조
송병석
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910022196A priority Critical patent/KR940010548B1/en
Publication of KR930014931A publication Critical patent/KR930014931A/en
Application granted granted Critical
Publication of KR940010548B1 publication Critical patent/KR940010548B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

이 발명은 패키지를 기판상에 실장하는 과정에서 온도변화에 의해 패키지내의 리드 프레임 패드 저면에 잔존해 있던 수분이 기화되어 수증기압을 발생시켜 패키지에 크랙을 유발시키는 것을 방지하기 위한 반도체 리드 프레임에 관한 것으로, 리드 프레임 제작시 리드 프레임 패드에 다수의 관통홀을 형성한 후 스웨징 가공처리하여 요홈을 형성함으로써 리드 프레임 패드와 지수지와의 결합력이 증대되고 접착력이 향상되어 박리현상을 방지할 수 있으므로 패키지 실장시 발생할 수 있는 패키지 크랙의 발생률을 감소시켜 제품의 품질 및 신뢰성을 향상시킬 수 있다.The present invention relates to a semiconductor lead frame for preventing moisture from remaining on the bottom surface of a lead frame pad in a package due to temperature changes during mounting of the package on a substrate to generate water vapor pressure to cause cracks in the package. When the lead frame is manufactured, a number of through holes are formed in the lead frame pad and then swaging to form grooves, thereby increasing the bonding force between the lead frame pad and the index paper and improving the adhesive force to prevent peeling. By reducing the incidence of package cracks that can occur during mounting, product quality and reliability can be improved.

또한 스탬핑 리드 프레임 구조를 제시함으로써 생산성 향상 및 원가절감을 할 수 있는 효과가 있다.In addition, by presenting a stamped lead frame structure, there is an effect that can improve productivity and reduce costs.

Description

반도체 리드 프레임Semiconductor leadframe

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4(가)∼(다)도는 이 발명에 따른 리드 프레임의 평면도와 Y-Y'선을 따라 절단한 단면도 및 부분확대도,4 (a) to (c) are a plan view of the lead frame according to the present invention, a cross-sectional view and a partially enlarged view taken along the line Y-Y ',

제5도는 이 발명에 따른 패키지의 단면 구조도이다.5 is a cross-sectional structural view of the package according to the present invention.

Claims (3)

중앙에 칩을 부착시킬 수 있는 리드 프레임 패드가 형성되고 이 패드의 양측으로 다수개의 리드가 배열형성된 반도체 리드 프레임에 있어서, 상기 리드 프레임 패드의 저면에 다수개 형성된 관통홀과 이 관통홀의 위나 아래에 1개 이상 스웨징 가공 처리에 의해 형성된 요홈들을 구비하여 이루어짐을 특징으로 하는 반도체 리드 프레임.In a semiconductor lead frame in which a lead frame pad capable of attaching a chip is formed at the center and a plurality of leads are arranged on both sides of the pad, a plurality of through holes formed on the bottom surface of the lead frame pad and above or below the through holes. A semiconductor lead frame comprising grooves formed by at least one swaging process. 제1항에 있어서, 상기 관통홀은 원형이나 다각형의 모든 형태를 포함함을 특징으로 하는 반도체 리드 프레임.The semiconductor lead frame as claimed in claim 1, wherein the through hole includes all shapes of a circle or a polygon. 제1항에 있어서, 관통홀에 스웨징 가공처리하여 요홈들을 형성시킨 구조는 리드 프레임 패드 및 리드 프레임의 모든 기능부를 포함할 수 있음을 특징으로 하는 반도체 리드 프레임.The semiconductor lead frame according to claim 1, wherein the structure in which the grooves are formed by swaging through-holes may include all of the lead frame pads and all functional parts of the lead frame. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910022196A 1991-12-05 1991-12-05 Semiconductor lead frame KR940010548B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910022196A KR940010548B1 (en) 1991-12-05 1991-12-05 Semiconductor lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910022196A KR940010548B1 (en) 1991-12-05 1991-12-05 Semiconductor lead frame

Publications (2)

Publication Number Publication Date
KR930014931A true KR930014931A (en) 1993-07-23
KR940010548B1 KR940010548B1 (en) 1994-10-24

Family

ID=19324185

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910022196A KR940010548B1 (en) 1991-12-05 1991-12-05 Semiconductor lead frame

Country Status (1)

Country Link
KR (1) KR940010548B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19732915C1 (en) * 1997-07-30 1998-12-10 Siemens Ag Manufacturing method for chip-module e.g. for credit card

Also Published As

Publication number Publication date
KR940010548B1 (en) 1994-10-24

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