KR970024063A - Multi-chip package in which circuit wiring is formed on die pad of lead frame - Google Patents

Multi-chip package in which circuit wiring is formed on die pad of lead frame Download PDF

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Publication number
KR970024063A
KR970024063A KR1019950038168A KR19950038168A KR970024063A KR 970024063 A KR970024063 A KR 970024063A KR 1019950038168 A KR1019950038168 A KR 1019950038168A KR 19950038168 A KR19950038168 A KR 19950038168A KR 970024063 A KR970024063 A KR 970024063A
Authority
KR
South Korea
Prior art keywords
circuit wiring
die pad
chip package
lead frame
adhesive
Prior art date
Application number
KR1019950038168A
Other languages
Korean (ko)
Inventor
박종영
김영대
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950038168A priority Critical patent/KR970024063A/en
Publication of KR970024063A publication Critical patent/KR970024063A/en

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 멀티 칩 패키지에 관한 것으로, 더욱 상세하게는 기판의 배선 회로를 리드프레임 제작 시에 리드프레임의 다이패드에 형성하여 패키지 제조 단가를 낮출 수 있게 하고 또한 이에 따른 회로 배선 기판의 삭제로 박형의 패키지를 제조할 수 있는 동시에 작업성이 용이한 패키지를 제조할 수 있는 것이다.The present invention relates to a multi-chip package, and more particularly, to form a wiring circuit of the substrate on the die pad of the lead frame at the time of manufacturing the lead frame to reduce the manufacturing cost of the package and to eliminate the circuit wiring board accordingly It is possible to manufacture a package can be manufactured at the same time easy workability of the package.

Description

회로 배선을 리드프레임의 다이패드 상에 형성한 멀티 칩 패키지Multi-chip package in which circuit wiring is formed on die pad of lead frame

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 3A도∼제 3F도는 본 발명에 의한 기판 상의 회로 배선의 형성 단계를 나타내는 공정도,3A to 3F are process drawings showing the step of forming circuit wiring on a substrate according to the present invention;

제 4도는 본 발명에 의한 회로 배선을 리드프레임의 다이패드 상에 형성한 멀티 칩 패키지를 나타내는 단면도.4 is a cross-sectional view showing a multi-chip package in which the circuit wiring according to the present invention is formed on a die pad of a lead frame.

Claims (4)

멀티 칩 패키지에 있어서, 리드프레임의 다이패드와, 그 다이패드의 일측면 상에 형성된 회로 배선 패턴들과, 그 회로 배선 패턴들 상에 접착된 복수개의 본딩 패드를 갖는 적어도 둘 이상의 칩과, 그 본딩 패드들에 각기 대응된 회로 배선 패턴들을 전기적 연결하는 1차 본딩 와이어와, 그 전기적 연결된 회로 배선 패턴들에 각기 대응되는 리드프레임의 리드들을 각기 전기적 연결하는 2차 본딩 와이어를 포함하는 것을 특징으로 하는 회로 배선을 리드프레임의 다이패드 상에 형성한 멀티 칩 패키지.A multi-chip package, comprising: at least two chips having a die pad of a leadframe, circuit wiring patterns formed on one side of the die pad, a plurality of bonding pads bonded on the circuit wiring patterns, and And a primary bonding wire electrically connecting the circuit wiring patterns respectively corresponding to the bonding pads, and a secondary bonding wire electrically connecting the leads of the lead frame respectively corresponding to the electrically connected circuit wiring patterns. The multi-chip package which formed the circuit wiring to be formed on the die pad of a lead frame. 제 1항에 있어서, 상기 다이패드와 상기 회로 배선 패턴이 접착제에 의해 접착된 것을 특징으로 하는 회로 배선을 리드프레임의 다이패드 상에 형성한 멀티칩 패키지.The multichip package according to claim 1, wherein the die pad and the circuit wiring pattern are bonded by an adhesive. 제 1항에 있어서, 상기 회로 배선 패턴과 칩을 접착한 접착제가 비 전도성인 것을 특징으로 하는 회로 배선을 리드프레임의 다이패드 상에 형성한 멀티 칩 패키지.The multi-chip package according to claim 1, wherein the circuit wiring pattern and the adhesive bonding the chip are non-conductive. 제 1항 또는 제 3항에 있어서, 상기 접착제가 폴리이미드 계열의 비전도성 접착제인 것을 특징으로 하는 회로 배선을 리드프레임의 다이패드 상에 형성한 멀티 칩 패키지.The multi-chip package according to claim 1 or 3, wherein the adhesive is a polyimide-based nonconductive adhesive. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950038168A 1995-10-30 1995-10-30 Multi-chip package in which circuit wiring is formed on die pad of lead frame KR970024063A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950038168A KR970024063A (en) 1995-10-30 1995-10-30 Multi-chip package in which circuit wiring is formed on die pad of lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950038168A KR970024063A (en) 1995-10-30 1995-10-30 Multi-chip package in which circuit wiring is formed on die pad of lead frame

Publications (1)

Publication Number Publication Date
KR970024063A true KR970024063A (en) 1997-05-30

Family

ID=66584909

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950038168A KR970024063A (en) 1995-10-30 1995-10-30 Multi-chip package in which circuit wiring is formed on die pad of lead frame

Country Status (1)

Country Link
KR (1) KR970024063A (en)

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