KR970030745A - Manufacturing method of multi-chip package with solder pre-plating lead frame - Google Patents

Manufacturing method of multi-chip package with solder pre-plating lead frame Download PDF

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Publication number
KR970030745A
KR970030745A KR1019950043189A KR19950043189A KR970030745A KR 970030745 A KR970030745 A KR 970030745A KR 1019950043189 A KR1019950043189 A KR 1019950043189A KR 19950043189 A KR19950043189 A KR 19950043189A KR 970030745 A KR970030745 A KR 970030745A
Authority
KR
South Korea
Prior art keywords
lead frame
manufacturing
substrate
solder
chip package
Prior art date
Application number
KR1019950043189A
Other languages
Korean (ko)
Inventor
김영대
서정우
정문채
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950043189A priority Critical patent/KR970030745A/en
Publication of KR970030745A publication Critical patent/KR970030745A/en

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Abstract

본 발명은 리드프에임을 적용한 멀티 칩 패키지의 제조방법에 관한 것으로, 외부리드 부분에 미리 솔더 프래팅된 리드프레임을 적용하여 패키지를 제조함으로써 제조 공정의 단순화와 자연 오염을 최소화로 할 수 있는 동시에 제조 단가를 낮출 수 있는 특징을 갖는다.The present invention relates to a method for manufacturing a multi-chip package using a lead frame, and by manufacturing a package by applying a solder-framed lead frame to an outer lead portion, the manufacturing process can be simplified and the natural contamination can be minimized. It has the characteristics which can reduce manufacturing cost.

Description

솔더 프리 프래팅 리드프레임(solder pre-plating lead frame)을 적용한 멀티 칩 패키지의 제조 방법Manufacturing method of multi-chip package with solder pre-plating lead frame

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 1도는 멀티 칩 패키지를 나타내는 단면도.1 is a cross-sectional view showing a multi-chip package.

Claims (3)

(a) 패턴닝된 기판을 준비하여 그 기판의 일측면과 적어도 하나 이상의 칩들을 접착하는 단계와, (b) 그 기판에 형성된 접속 단자들과 실장된 칩들의 본딩 패드들을 각기 대응되도록 전기적 연결하는 단계와, (c) 그 접속 단자들과 상기 기판 상에 형성된 회로 패턴들에 의해 각기 전기적 연결된 기판 본딩 패드들에 대응된 리드프에임의 내부리드들을 전기적 연결하는 단계와, (d)상기 전기적 연결 부분을 성형하는 단계와, (e)디드래쉬 및 외부리드 절단/절곡을 하는 단계와, (f) 그 외부리드들에 솔더 프래팅을 하는 단계를 포함하는 멀티 칩 패키지 제조방법에 있어서, 상기 (a)(b)(c)(d)단계의 리드프레임의 외부리드들이 솔더 프래팅 되어 있으며, 상기 (e)단계의 디프래쉬 하는 단계가 제거되는 것을 특징으로 하는 솔더 프리 프래팅 리드프레임(solder pre-plating lead frame)을 적용한 멀티 칩 패키지의 제조 방법.(a) preparing a patterned substrate and adhering at least one chip to one side of the substrate; and (b) electrically connecting the connection terminals formed on the substrate to the bonding pads of the mounted chips. (C) electrically connecting the inner leads of the leadframe corresponding to the substrate bonding pads respectively electrically connected by the connection terminals and the circuit patterns formed on the substrate, and (d) the electrical connection. A method of manufacturing a multi-chip package comprising the steps of forming a part, (e) de-dlashing and cutting and bending the outer lead, and (f) soldering the outer leads. a) (b) (c) and (d) the outer lead of the lead frame is solder-printed, the solder pre-printed lead frame (solder) characterized in that the step of defreshing the step (e) is removed pre-plating Manufacturing method of multi chip package with lead frame). 제 1항에 있어서, 상기 (c) 단계의 기판 본딩 패드들과 내부리드들을 전기적 연결하는 수단이 전도성이 양호한 재질의 범프인 것을 솔더 프리 프래팅 리드프레임을 적용한 멀티 칩 패키지의 제조 방법.The method of claim 1, wherein the means for electrically connecting the substrate bonding pads and the inner leads of the step (c) is a bump of a good conductive material. 제 2항에 있어서, 상기 범프의 재질이 금 그리고 솔더 중의 어느 하나인 것을 특징으로 하는 솔더 프리 프래팅 리드프레임을 적용한 멀티 칩 패키지의 제조 방법.3. The method of claim 2, wherein the bump is made of one of gold and solder. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950043189A 1995-11-23 1995-11-23 Manufacturing method of multi-chip package with solder pre-plating lead frame KR970030745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950043189A KR970030745A (en) 1995-11-23 1995-11-23 Manufacturing method of multi-chip package with solder pre-plating lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950043189A KR970030745A (en) 1995-11-23 1995-11-23 Manufacturing method of multi-chip package with solder pre-plating lead frame

Publications (1)

Publication Number Publication Date
KR970030745A true KR970030745A (en) 1997-06-26

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ID=66588713

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950043189A KR970030745A (en) 1995-11-23 1995-11-23 Manufacturing method of multi-chip package with solder pre-plating lead frame

Country Status (1)

Country Link
KR (1) KR970030745A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101231802B1 (en) * 2011-07-06 2013-02-08 엘에스파워세미텍 주식회사 System and method for heterojunction without contacting a heating source

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101231802B1 (en) * 2011-07-06 2013-02-08 엘에스파워세미텍 주식회사 System and method for heterojunction without contacting a heating source

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