KR930009028A - Semiconductor package using interconnect lead and manufacturing method thereof - Google Patents

Semiconductor package using interconnect lead and manufacturing method thereof Download PDF

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Publication number
KR930009028A
KR930009028A KR1019910017974A KR910017974A KR930009028A KR 930009028 A KR930009028 A KR 930009028A KR 1019910017974 A KR1019910017974 A KR 1019910017974A KR 910017974 A KR910017974 A KR 910017974A KR 930009028 A KR930009028 A KR 930009028A
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KR
South Korea
Prior art keywords
lead
semiconductor chip
semiconductor package
interconnect
inner lead
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KR1019910017974A
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Korean (ko)
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KR940008329B1 (en
Inventor
김영선
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문정환
금성일렉트론 주식회사
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Priority to KR1019910017974A priority Critical patent/KR940008329B1/en
Publication of KR930009028A publication Critical patent/KR930009028A/en
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Publication of KR940008329B1 publication Critical patent/KR940008329B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Abstract

본 고안은 인터컨넥트 리드를 이용한 반도체 패키지 및 그 제조방법에 관한 것으로 반도체칩의 중앙부에 구비된 복수개의 본드패드와 리드프레임의 인너리드를 전기적으로 접속 연결하고 봉합하여 구성하는 반도체 패키지에 있어서, 상기 인너리드를 짧게 형성하고 그 인너리드와 반도체칩의 본드패드를 전기적으로 접속연결시키기 위한 인터컨넥트 리드를 상기 반도체칩의 상면에 부착하여 구성함을 특징으로 하고 있으며, 상기 인너컨넥트 리드는 상, 하절연판의 사이에 반도체칩의 본드패드와 연결되는 내부리드와, 리드프레임의 인너리드와 연결되는 외부리드가 구비된 복수개의 전도성 리드가 형성되어 있다.The present invention relates to a semiconductor package using an interconnect lead and a method of manufacturing the same. A semiconductor package comprising a plurality of bond pads provided at a central portion of a semiconductor chip and an inner lead of a lead frame, wherein the semiconductor package is electrically connected and sealed. An interconnect lead is formed on the upper surface of the semiconductor chip to shorten the inner lead and electrically connect the inner lead and the bond pad of the semiconductor chip. A plurality of conductive leads including an inner lead connected to the bond pad of the semiconductor chip and an outer lead connected to the inner lead of the lead frame are formed between the insulating plates.

이와같이 구성되는 본 발명은 리드프레임의 인너리드가 짧아 리드의 평면도 문제를 해결할 수 있고 제조공정이 단축되며 다핀의 DiP타입 패키지를 실현할 수 있는 등의 효과가 있다.The present invention configured as described above has the effect of shortening the inner lead of the lead frame to solve the plan problem of the lead, shortening the manufacturing process, and realizing a multi-pin DiP type package.

Description

인터컨넥트 리드를 이용한 반도체 패키지 및 그 제조방법Semiconductor package using interconnect lead and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 인터컨넥트 리드(interconncet-lid)를 이용한 반도체 패키지의 구성도,2 is a configuration diagram of a semiconductor package using an interconnect lead according to the present invention;

제3도는 본 발명에 사용되는 인터컨넥트 리드의 구성을 보이는 평면도.3 is a plan view showing the configuration of the interconnect lead used in the present invention.

Claims (7)

반도체칩(11)의 중앙부에 구비된 복수개의 본드패드(12)와 리드프레임의 인너리드(13)를 전기적으로 접속 연결하고 봉합하여 구성하는 반도체 패키지에 있어서, 상기 인너리드(13)를 짧게 형성하고 그 인너리드(13)와 반도체칩(11)의 본드패드(12)를 전기적으로 접속연결시키기 위한 인터컨넥트리드(14)를 상기 반도체칩(11)의 상면에 부착하여 구성함을 특징으로 하는 인터컨넥트 리드를 이용한 반도체 패키지.In the semiconductor package formed by electrically connecting, connecting and sealing the plurality of bond pads 12 provided in the center portion of the semiconductor chip 11 and the inner lead 13 of the lead frame, the inner lead 13 is formed to be short. And an interconnect 14 for electrically connecting and connecting the inner lead 13 and the bond pad 12 of the semiconductor chip 11 to the upper surface of the semiconductor chip 11. Semiconductor package using interconnect leads. 제1항에 있어서, 상기 인너컨넥트리드(14)는 상, 하절연판(15), (16)의 사이에 반도체칩(11)의 본드패드(12)와 연결되는 내부리드(17a)와, 리드프레임의 인너리드(13)와 연결되는 외부리드(17b)가 구비된 복수개의 전도성 리드(17)가 형성된 것임을 특징으로 하는 인터컨넥트 리드를 이용한 반도체 패키지.The inner connector (14) of claim 1, wherein the inner connect (14) includes an inner lead (17a) connected to the bond pads (12) of the semiconductor chip (11) between the upper and lower insulating plates (15) and (16). A semiconductor package using an interconnect lead, characterized in that a plurality of conductive leads (17) having an outer lead (17b) connected to the inner lead (13) of the frame is formed. 제2항에 있어서, 상기 상, 하절연판(15), (16)의 재질은 각 전도성리드(17)들을 절연시킬 수 있도록 폴리이미드계 수지 또는, 코팅액으로 형성됨을 특징으로 하는 인터컨넥트 리드를 이용한 반도체 패키지.The interconnect lead according to claim 2, wherein the upper and lower insulating plates 15 and 16 are made of polyimide resin or a coating liquid to insulate the conductive leads 17. Semiconductor package. 제2항에 있어서, 상기 전도성리드(17)의 재질은 리드프레임의 재질과 동일한 것임을 특징으로 하는 인터컨넥트 리드를 이용한 반도체 패키지.3. The semiconductor package according to claim 2, wherein the material of the conductive lead (17) is the same as that of the lead frame. 제2항에 있어서, 상기 전도성리드(17)의 재질은 알루미늄 또는 골드인 것을 특징으로 하는 인터컨넥트 리드를 이용한 반도체 패키지.3. The semiconductor package according to claim 2, wherein the conductive lead (17) is made of aluminum or gold. 반도체 패키지 제조방법에 있어서, 반도체칩(11)의 양측으로 인접하게 리드프레임의 인너리드(13)를 피딩시키는 공정과, 상기 반도체칩(11)의 상면에 인터컨넥트리드(14)를 부착시키는 공정과, 상기 반도체칩(11)의 본드패드(12)와 리드프레임의 인너리드(13)를 전기적으로 접속연결시키는 본딩공정과, 상기 반도체칩(11)과 리드프레임의 아웃리드(19)를 포함하는 일정부위를 밀폐시키는 봉합공정과, 통상적인 트리밍/포밍공정 및 플래팅 공정을 포함하여 제작됨을 특징으로 하는 인터컨넥트 리드를 이용한 반도체 패키지 제조방법.In the method of manufacturing a semiconductor package, a step of feeding the inner lead 13 of the lead frame adjacent to both sides of the semiconductor chip 11, and the step of attaching the interconnect 14 to the upper surface of the semiconductor chip 11 And a bonding process for electrically connecting and bonding the bond pad 12 of the semiconductor chip 11 and the inner lead 13 of the lead frame, and the semiconductor chip 11 and the out lead 19 of the lead frame. Method for manufacturing a semiconductor package using an interconnect lead characterized in that it comprises a sealing process for sealing a certain portion to be made, including a conventional trimming / forming process and a plating process. 제6항에 있어서, 상기 인터컨넥트리드(14) 제조방법은 비전도성 재질을 이용하여 하부절연판(16)을 형성하는 공정과, 그 하부 절연판(16)위에 전도성 금속으로 미들플레이트(20)를 형성하는 공정과, 그 미들플레이트(20)에 포토/에치방법으로 복수개의 와이어 또는 리드를 형성하는 공정과, 그위에 비전도성 재질을 이용하여 상부 절연판(15)을 형성하는 공정과, 적용할 칩사이즈 및 본드패드(12)의 위치에 맞게 포토/에치방법으로 모양을 형성하는 공정과, 적용할 패키지 사이즈에 맞게 레이저 등으로 커팅하는 공정을 포함하여 제작됨을 특징으로 하는 인터컨넥트 리드를 이용한 반도체 패키지 제조방법.The method of claim 6, wherein the method of manufacturing the interconnect 14 comprises forming a lower insulating plate 16 using a non-conductive material, and forming a middle plate 20 of a conductive metal on the lower insulating plate 16. A process of forming a plurality of wires or leads on the middle plate 20 by a photo / etch method, a process of forming an upper insulating plate 15 using a non-conductive material thereon, and a chip size to be applied. And a process of forming a shape by a photo / etch method according to the position of the bond pad 12 and a process of cutting with a laser or the like according to a package size to be applied. Way. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910017974A 1991-10-12 1991-10-12 Semiconductor package using inter connect lead and manufacturing method thereof KR940008329B1 (en)

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KR1019910017974A KR940008329B1 (en) 1991-10-12 1991-10-12 Semiconductor package using inter connect lead and manufacturing method thereof

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KR930009028A true KR930009028A (en) 1993-05-22
KR940008329B1 KR940008329B1 (en) 1994-09-12

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