KR960002344Y1 - Semiconductor package - Google Patents
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- KR960002344Y1 KR960002344Y1 KR92022708U KR920022708U KR960002344Y1 KR 960002344 Y1 KR960002344 Y1 KR 960002344Y1 KR 92022708 U KR92022708 U KR 92022708U KR 920022708 U KR920022708 U KR 920022708U KR 960002344 Y1 KR960002344 Y1 KR 960002344Y1
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- semiconductor package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
내용 없음.No content.
Description
제1도는 일반적인 반도체 패키지의 구조를 보인 종단면도1 is a longitudinal sectional view showing a structure of a general semiconductor package
제2도 내지 제5도는 본 고안에 의한 반도체 패키지를 설명하기 위한 도면으로서,2 to 5 are views for explaining a semiconductor package according to the present invention,
제2도는 본 고안 반도체 패키지의 전체 구조를 보인 종단면도이고,Figure 2 is a longitudinal cross-sectional view showing the overall structure of the semiconductor package of the present invention,
제3도는 본 고안 제1, 제2 반도체칩의 본딩전 상태를 보인 사시도이며,3 is a perspective view showing a state before bonding of the first and second semiconductor chips of the present invention,
제4도는 본 고안 제1, 제2 반도체칩의 본딩공정을 도시한 단면도이고4 is a cross-sectional view illustrating a bonding process of the first and second semiconductor chips of the present invention.
제5도는 본 고안에 사용되는 신호연결부재의 평면도이다.5 is a plan view of the signal connection member used in the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11, 12 : 제1,제2반도체칩 13 : 신호연결부재11, 12: first and second semiconductor chip 13: signal connection member
13a : 신호연결리드 13-1 : 인너리드부13a: Signal connection lead 13-1: Inner lead part
13-2 : 아웃리드부 14 : 몰드수지13-2: Out lead part 14: Mold resin
본 고안은 단일 패키지내에 2개 이상의 반도체칩을 내장하여 구성하는 반도체 패키지에 관한 것으로, 특히 소자의 동작속도 향상 및 실장밀도 향상을 도모한 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package comprising two or more semiconductor chips in a single package, and more particularly, to a semiconductor package aimed at improving the operation speed and mounting density of devices.
일반적으로 반도체 패키지는 제1도에 도시한 바와 같이, 반도체칩(1)을 리드프레임의 패들(2)위에 접착제(3)를 개재하여 부착하고, 상기 칩(1)과 리드르레임의 인너리드(4)를 금속와이어(5)를 이용하여 전기적으로 접속연결시킨 후 이와 같이된 칩(1)과 리드프레임의 인너리드(4)를 포함하는 일정면적을 에폭시수지(6)로 몰딩하여 패키지 몸체를 형성한 다음, 패키지 몸체의 양외측으로 돌출된 아웃리드(7)를 소정형태로 절곡형성하는 트림/포밍공정을 행하여 구성하게 된다.In general, as shown in FIG. 1, the semiconductor package attaches the semiconductor chip 1 to the paddle 2 of the lead frame through the adhesive 3, and the inner lead of the chip 1 and the lead rail. (4) is electrically connected and connected using a metal wire (5) and then molded a certain area including the chip (1) and the inner lead (4) of the lead frame with an epoxy resin (6) package body Next, the trimmer is formed by performing a trim / forming process of bending the outlead 7 protruding outwardly of the package body into a predetermined shape.
이와 같이 구성된 반도체 패키지는 패키지 몸체의 양외측으로 돌출된 아웃리드(7)들을 기판에 솔더링하는 것에 의하여 실장되어 소기의 동작을 하게 된다.The semiconductor package configured as described above is mounted by soldering the outleads 7 protruding to both sides of the package body to the substrate to perform a desired operation.
그러나, 상기한 바와 같은 종래의 반도체 패키지는 하나의 패키지내에 하나의 칩만을 내장시키는 구조로서 실장밀도가 낮고, 금속와이어에 의해 칩(1)과 리드(4)가 전기적으로 접속되므로 전기적 경로가 길어 소자의 전기적인 특성에 좋지 않게 되며, 칩(1)의 본드패드와 리드프레임의 인너리드(4)부 각각을 순차적으로 접속하여야 함에 따라 공정시간이 길어지게 되어 생산성이 저하되는 단점이 있었다.However, the conventional semiconductor package as described above has a low mounting density because only one chip is embedded in one package, and the electrical path is long because the chip 1 and the lead 4 are electrically connected by metal wires. It is not good for the electrical characteristics of the device, because the bond pad of the chip (1) and each of the inner lead (4) of the lead frame must be sequentially connected, the process time is long, there is a disadvantage that the productivity is lowered.
이를 감안하여 안출한 본 고안의 목적온 단일 패키지내에 2개이상의 반도체칩을 내장하여 구성함으로써 실장밀도 향상 및 동작스피드 개선을 도모한 반도체 패키지를 제공함에 있다.In view of this, it is an object of the present invention to provide two or more semiconductor chips in a single package, thereby providing a semiconductor package for improving mounting density and operating speed.
본 고안의 다른 목적은 칩대칩 및 칩대리드의 전기적인 접속을 금속와이어가 아닌 솔더범프를 매개로 일괄본딩함으로써 소자의 정기적인 특성을 좋게하고, 공정시간을 단축시킬 수 있도록 한 반도체 패키지를 제공함에 있다.Another object of the present invention is to provide a semiconductor package that improves the periodic characteristics of the device and shortens the processing time by collectively bonding the electrical connection of chip-to-chip and chip-to-lead through solder bumps instead of metal wires. have.
상기와 같은 본 고안의 목적을 달성하기 위하여, 2이상의 반도체칩을 내장하는 것에 있어서, 양측변부에 다수의 도전범프를 가지는 제1반도체칩 및 이 제1반도체칩에 적층되며 접촉면에는 제1반도체칩의 도전범프 배열과 직교하는 방향으로 다수의 도전범프가 배열된 제2반도체칩과 상기 제1, 제2반도체칩 사이에 개재되어 칩의 전기적인 신호를 외부로 전달하는 신호연결부재를 구비하여 반도체칩의 각 도전범프와 신호연결부재의 각 인너리드부를 열압착 본딩하고, 상기 제1, 제2반도체칩과 신호연결부재의 인너리드부를 포함하는 일정면적을 몰드수지로 몰딩하여 구성함을 특징으로 하는 반도체 패키지가 제공된다.In order to achieve the object of the present invention as described above, in embedding two or more semiconductor chips, a first semiconductor chip having a plurality of conductive bumps on both sides and the first semiconductor chip is laminated on the first semiconductor chip, the contact surface on the first semiconductor chip A semiconductor having a second semiconductor chip in which a plurality of conductive bumps are arranged in a direction orthogonal to the conductive bump array of the semiconductor chip, and a signal connection member interposed between the first and second semiconductor chips to transmit an electrical signal of the chip to the outside Thermo-compression bonding each conductive bump of the chip and each of the inner lead portions of the signal connection member, and molding a predetermined area including the inner lead portions of the first and second semiconductor chips and the signal connection member with a mold resin. A semiconductor package is provided.
이하, 상기한 바와 같은 본 고안에 의한 반도체 패키지를 첨부도면에 의거하여 보다 상세히 실망한다.Hereinafter, the semiconductor package according to the present invention as described above is disappointed in more detail based on the accompanying drawings.
제2도는 본 고안 반도체 패키지의 전체구조를 보인 종단면도이고, 제3도 및 제4도는 본 고안 제1, 제2반도체칩의 본딩전 상태를 보인 사시도 및 본딩공정을 보인 단면도이며, 제5도는 본 고안에 사용되는 신호연결부재의 평면도로서 이에 도시한 바와 같이, 본 고안에 의한 반도체 패키지는 단일패키지내에 2개이상의 반도체칩을 내장하여 구성함을 특징으로 하고 있다.2 is a longitudinal cross-sectional view showing the overall structure of the semiconductor package of the present invention, and FIGS. 3 and 4 are cross-sectional views showing a perspective view and a bonding process of the first and second semiconductor chips of the present invention before bonding, and FIG. As a plan view of the signal connection member used in the present invention, as shown therein, the semiconductor package according to the present invention is characterized in that two or more semiconductor chips are built in a single package.
보다 상세히 살펴보면, 본 고안 반도체 패키지는 제1반도체칩(11) 및 이 반도체칩(12)에 적층되는 제2반도체칩(12)과, 상기 제1, 제2반도체칩(11)(12) 사이에 개재되어 칩의 신호를 외부로 전달하는 신호연결부재(13)와, 상기 제1, 제2반도체칩(11)(12)과 신호연결부재(13)의 인너리드부(13-1)를 포함하는 일정면적을 밀봉하여 패키지 몸체를 형성하는 몰드수지(14)로 크게 구성된다.In more detail, the inventive semiconductor package includes a first semiconductor chip 11 and a second semiconductor chip 12 stacked on the semiconductor chip 12, and between the first and second semiconductor chips 11 and 12. A signal connection member 13 interposed therebetween for transmitting a signal of the chip to the outside, and an inner lead portion 13-1 of the first and second semiconductor chips 11 and 12 and the signal connection member 13; It is largely composed of a mold resin 14 to seal the predetermined area to form a package body.
상기 제1, 제2반도체칩(11)(12)의 양측변부에는 소정높이로 도전범프(11a)(12a)가 형성되는 바, 상호 직교되는 방향으로 형성되어 배열되고, 이 칩(11)(12)들은 그들의 도전범프(11a)(12a)가 마주보도록 결합되어 적층되며, 상기 칩(11)(12) 사이에는 신호연결부재(13)가 개재된다.Conductive bumps 11a and 12a are formed at both sides of the first and second semiconductor chips 11 and 12 at predetermined heights, and are formed and arranged in directions perpendicular to each other. 12 are stacked in such a manner that their conductive bumps 11a and 12a face each other, and a signal connection member 13 is interposed between the chips 11 and 12.
상기 신호연결부재(13)는 칩(11)(12)의 도전범프(11a)(12a)에 본딩되는 인너리드부(13-1)와 기판(도시되지 않음)에 접속되는 아웃리드부(13-2)가 일체로 형성된 복수개의 신호연결리드(13a)들로 구성되는바, 제5도에 도시한 바와 같이, 제1반도체칩(11) 접속용 리드군과, 제2반도체칩(12) 접속용 리드군의 조합으로 이루어진다.The signal connection member 13 includes an inner lead portion 13-1 bonded to the conductive bumps 11a and 12a of the chips 11 and 12 and an out lead portion 13 connected to a substrate (not shown). -2) is composed of a plurality of signal connection leads 13a formed integrally, as shown in FIG. 5, the lead group for connecting the first semiconductor chip 11 and the second semiconductor chip 12 It consists of a combination of lead groups for connection.
여기서, 상기 신호연결부재(13)는 금속재질로 형성된 다수개의 신호연결리드(13a)들로 구성되나, 이에 한정하는 것은 아니고, 상기한 형태의 리드이외에도, 상, 하에 도전패턴이 형성된 세라믹기판(Seramic Substrate)이나, 또는 상, 하부에 도전패턴이 형성된 탭테이프(TAB Tape)를 이용하여 구성할 수도 있다.Here, the signal connection member 13 is composed of a plurality of signal connection leads 13a formed of a metal material, but is not limited thereto, and in addition to the above-described lead, a ceramic substrate having conductive patterns formed on top and bottom ( It is also possible to use Seramic Substrate or a TAB Tape having conductive patterns formed on top and bottom thereof.
이와 같이 구성된 본 고안에 의한 반도체 패키지를 제작함에 있어서는 먼저 각 반도체칩(11)(12)의 상면 양측에 솔더 또는 골드(Gold)등과 같은 도전성의 금속으로 도전범프(11a)(12a)를 형성하는 바, 이는 일렉트로플래팅(Electroplating) 방법, 증착(Evaporating)방법 및 스터드범프(Stud Bump) 방법으로 도전범프(11a)(12a)를 형성한다.In fabricating the semiconductor package according to the present invention configured as described above, first, the conductive bumps 11a and 12a are formed of conductive metals such as solder or gold on both sides of the upper surfaces of the semiconductor chips 11 and 12. This forms the conductive bumps 11a and 12a by an electroplating method, an evaporating method, and a stud bump method.
이후, 도전범프(11a)(12a)가 형성된 반도체칩(11)(12)을 그 사이에 신호연결부재(13)를 개재하여 도전범프(11a)(12a)가 마주보도록 맞대어 결합시키는 바, 각 반도체칩(11)(12)의 도전범프(11a)(12a)들에 신호연결부재(13)의 각 신호연결리드(13a)들의 인너리드(13-l)부를 일치시켜 열압착 본딩하여 전기적으로 접속연결시킨다.Thereafter, the semiconductor chips 11 and 12 on which the conductive bumps 11a and 12a are formed are joined to each other so that the conductive bumps 11a and 12a face each other through the signal connection member 13 therebetween. The conductive bumps 11a and 12a of the semiconductor chip 11 and 12 coincide with the inner lead 13-1 portions of the signal connection leads 13a of the signal connection member 13 to be electrically pressed and thermally bonded. Connect.
이러한 본딩공정은 히팅프레스(15)(16)를 이용하여 상. 하에서 압력과 온도를 가하면서 본딩하는 방법 및 보다 확실한 본딩을 위하여 상. 하부에서 압력과 온도를 가함과 동시에 측면에서 초음파를 가하는 방법등으로 일광본딩(Gang Bonding)한다.This bonding process is performed by using the heating press 15, 16. How to bond under pressure and temperature under pressure and phases for more reliable bonding. Gang Bonding is applied by applying pressure and temperature at the bottom and ultrasonic at the side.
이후 본딩된 상기 칩(11)(12)과 신호연결부재(13)의 인너리드부(13-1)를 포함하는 일정면적을 몰드수지(14)로 몰딩하여 패키지 몸체를 형성하고, 그 몸체의 외부로 돌출된 아웃리드부(13-2)를 소정형태로 절곡형성하여 제2도와 같은 반도체칩 패키지를 제작하게 된다.Thereafter, a predetermined area including the bonded chip 11 and 12 and the inner lead portion 13-1 of the signal connection member 13 is molded with a mold resin 14 to form a package body, and A semiconductor chip package as shown in FIG. 2 is manufactured by bending the outlead portion 13-2 protruding to the outside into a predetermined shape.
이상에서 상세히 설명한 바와 같이, 본 고안에 의한 반도체칩 패키지는 단일패키지내에 여러개의 칩이 내장되어 구성되므로 패키지 실장밀도가 증가되고, 보다 다양한 형태의 실장이 가능하게 되며(이는 탭테이프로 구성한 신호연결부재 채용시) 도전범프에 의한 직접적인 접속으로 칩의 패드와 리드간의 전기적 접속경로가 단축되어 소자의 전기적인 특성이 향상, 즉 노이즈 및 저항감소의 효과가 있고, 기존의 다이본딩공정이 제거될 뿐만아니라 칩과 리드를 일괄본딩하게 되므로 종래의 패키지 제조공정에 비해 제조공정시간이 단축된다는 효과도 있다. 따라서 생산성 향상을 기할 수 있는 것이다.As described in detail above, the semiconductor chip package according to the present invention is composed of a plurality of chips embedded in a single package, so that the package mounting density is increased and more various types of mounting are possible (this is a signal connection composed of tap tapes). When the member is used), the direct connection by the conductive bump shortens the electrical connection path between the pad and the lead of the chip, thereby improving the electrical characteristics of the device, that is, reducing the noise and resistance, and eliminating the existing die bonding process. Since the chip and the lead are bonded together, the manufacturing process time is shortened as compared with the conventional package manufacturing process. Therefore, productivity can be improved.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92022708U KR960002344Y1 (en) | 1992-11-18 | 1992-11-18 | Semiconductor package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92022708U KR960002344Y1 (en) | 1992-11-18 | 1992-11-18 | Semiconductor package |
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| Publication Number | Publication Date |
|---|---|
| KR940013678U KR940013678U (en) | 1994-06-25 |
| KR960002344Y1 true KR960002344Y1 (en) | 1996-03-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR92022708U KR960002344Y1 (en) | 1992-11-18 | 1992-11-18 | Semiconductor package |
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| Country | Link |
|---|---|
| KR (1) | KR960002344Y1 (en) |
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1992
- 1992-11-18 KR KR92022708U patent/KR960002344Y1/en not_active IP Right Cessation
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| KR940013678U (en) | 1994-06-25 |
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