KR100325242B1 - Semiconductor device and fabricating method thereof - Google Patents
Semiconductor device and fabricating method thereof Download PDFInfo
- Publication number
- KR100325242B1 KR100325242B1 KR1019980017694A KR19980017694A KR100325242B1 KR 100325242 B1 KR100325242 B1 KR 100325242B1 KR 1019980017694 A KR1019980017694 A KR 1019980017694A KR 19980017694 A KR19980017694 A KR 19980017694A KR 100325242 B1 KR100325242 B1 KR 100325242B1
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- South Korea
- Prior art keywords
- pcb
- pattern
- semiconductor chip
- die
- copper foil
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 238000000034 method Methods 0.000 title claims abstract description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 59
- 229910052802 copper Inorganic materials 0.000 claims abstract description 25
- 239000010949 copper Substances 0.000 claims abstract description 25
- 239000007788 liquid Substances 0.000 claims abstract description 18
- 238000007747 plating Methods 0.000 claims abstract description 13
- 239000011889 copper foil Substances 0.000 claims description 32
- 238000004519 manufacturing process Methods 0.000 claims description 20
- 239000011347 resin Substances 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 8
- 238000004806 packaging method and process Methods 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 238000005553 drilling Methods 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000005476 soldering Methods 0.000 claims description 2
- SXHLTVKPNQVZGL-UHFFFAOYSA-N 1,2-dichloro-3-(3-chlorophenyl)benzene Chemical compound ClC1=CC=CC(C=2C(=C(Cl)C=CC=2)Cl)=C1 SXHLTVKPNQVZGL-UHFFFAOYSA-N 0.000 description 2
- XLDBTRJKXLKYTC-UHFFFAOYSA-N 2,3,4,4'-tetrachlorobiphenyl Chemical compound C1=CC(Cl)=CC=C1C1=CC=C(Cl)C(Cl)=C1Cl XLDBTRJKXLKYTC-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000009417 prefabrication Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 239000005028 tinplate Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체소자에 관한 것으로, 보다 상세하게는 반도체칩을 탑재하여 패키징하던 리드프레임(leadframe) 대신에 피시비(PCB : Printed Circuit Board)를 이용해서 제작되는 반도체소자 및 그 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device manufactured by using a printed circuit board (PCB) instead of a leadframe packaged with a semiconductor chip and a structure thereof.
도 1은 리드프레임을 이용한 종래의 반도체소자 제작과정을 순서대로 보이고 있는 공정흐름도로서, 이 도면을 참조하여 제작과정을 살펴보면, 먼저, 도 1a와 같이 준비된 리드프레임(10)의 다이(die;11) 위에 도 1b와 같이 반도체칩(13)를 다이본딩하고, 이어서 다이본딩된 반도체칩(13)의 본딩패드(도시되지 않음)와 다이(11)의 양측에 형성된 복수의 리드(lead;12)를 와이어(14)를 이용해서 도 1c와 같이 선택적으로 와이어본딩한 다음, 수지를 이용하여 상기 반도체칩이 탑재된 다이 및 리드를 도 1d와 같이 소정크기로 몰드(mold;15)하여 반도체소자를 패키징하게 된다. 이때 몰딩과정에서 상기 도 1d에서 보인 바와 같이 패키지의 외측에 수지잔류물(16)이 잔재하게 되므로 세척공정을 통해 도 1e와 같이 이를 세척한 다음, 외측에 노출되어 있는 리드프레임에 도 1f와 같이 틴 플레이팅(TIN Plating;17)을 한 다음, 도 1g와 같이 트리밍(trimming) 및 포밍(forming)하여 반도체소자가 제작되어 진다.FIG. 1 is a process flow chart showing a conventional semiconductor device fabrication process using a lead frame in order. Referring to the fabrication process with reference to this drawing, first, a die 11 of a lead frame 10 prepared as shown in FIG. Die bonding the semiconductor chip 13 as shown in FIG. 1B, and then bonding pads (not shown) of the die-bonded semiconductor chip 13 and a plurality of leads 12 formed on both sides of the die 11. Is selectively wire-bonded using the wire 14 as shown in FIG. 1C, and then a die and lead on which the semiconductor chip is mounted are molded into a predetermined size as shown in FIG. 1D by using a resin to form a semiconductor device. Will be packaged. At this time, since the resin residue 16 remains on the outside of the package as shown in FIG. 1D during the molding process, the resin residue 16 is washed as shown in FIG. 1E through a washing process, and then the lead frame exposed to the outside is shown in FIG. 1F. After tin plating 17, the semiconductor device is fabricated by trimming and forming the substrate as illustrated in FIG. 1G.
그러나, 상기와 같이 리드프레임을 이용한 종래의 반도체소자의 제작과정은 복잡한 공정을 거치게 되므로 제작기간이 길어 지고 제작비용이 증가하는 문제가 있다.However, the manufacturing process of the conventional semiconductor device using the lead frame as described above has a problem that the manufacturing period is long and the manufacturing cost increases because it goes through a complicated process.
본 발명의 목적은 상기한 문제를 감안하여 창안한 것으로, 리드프레임 대신에 피씨비를 이용하여 반도체칩을 패키징함으로서 반도체소자를 제작할 수 있는 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention was devised in view of the above-described problems, and an object thereof is to provide a method for manufacturing a semiconductor device by packaging a semiconductor chip using PCB instead of a lead frame.
또, 본 발명의 다른 목적은 반도체칩을 패키징하기 위한 피씨비 패턴형태 및 그 구조를 제공하는데 있다.Another object of the present invention is to provide a PCB pattern form and its structure for packaging a semiconductor chip.
상기한 목적을 달성하기 위한 본 발명에 따른 반도체소자 탑재용 피씨비는 준비된 소정의 피씨비 상에 액체상태의 동을 이용하여 동박을 형성시킬 때 배면쪽으로 액상의 동이 흘러 소정형태의 동박패턴을 형성시킬 수 있도록 사각형상의 도금통로를 천공하고, 액상의 동을 피씨비 상에 흘려 피씨비의 전면에 동박을 형성함과 동시에 상기 사각형상의 도금통로를 통해 흘러 들어간 액상의 동에 의해 소정형태의 동박을 배면에 형성한 다음, 소정형태의 동박이 형성된 피씨비에 반도체칩을 탑재하여 본딩할 수 있는 형태로 피씨비의 다이 및 리드패턴을 형성하고, 상기 소정형태의 동박이 형성된 피씨비를 반도체칩이 탑재될 수 있는 형태로 피씨비패턴을 형성한 다음, 상기 피씨비 상의 각 동박패턴 소정부위에 원형의 구멍을 천공하여 제작되는 것을 특징으로 한다.In order to achieve the above object, the semiconductor device-mounting PCB according to the present invention may form a copper foil pattern having a predetermined shape by flowing liquid copper toward the back side when forming copper foil using liquid copper on a predetermined PCB. Perforated rectangular plating passage so as to flow the liquid copper on the PCB to form a copper foil on the front of the PCB and at the same time formed a copper foil of a predetermined shape by the liquid copper flowing through the rectangular plating passage. Next, a die and lead pattern of the PCB is formed in a form in which the semiconductor chip is bonded to the PCB on which the copper foil of a predetermined form is formed, and the PCB in which the copper foil of the predetermined form is formed is formed in a form in which the semiconductor chip can be mounted. After forming a pattern, it is produced by drilling a circular hole in a predetermined portion of each copper foil pattern on the PCB It shall be.
또, 본 발명의 다른 목적을 달성하기 위한 반도체소자 탑재용 피씨비는 피씨비의 전면에 반도체칩을 탑재하기 위하여 동박패터닝된 반도체칩 탑재용 다이패턴과, 상기 다이패턴에 탑재되는 반도체칩을 전기적으로 연결할 수 있도록 와이어를 본딩할 수 있게 동박을 패터닝하여 형성된 복수의 리드패턴과, 소자의 표면실장을 위한 솔더링시 외부소자와의 전기적 연결을 위하여 상기 다이패턴 및 복수의 리드패턴을 이루고 있는 동박이 피씨비의 측면을 각각 감싸면서 피씨비의 배면 부위까지 연장되어 이루어진 소정형태의 솔더패턴들이 각각 형성된 구조로 되며, 상기 각 패턴의 소정부위에 홀이 천공되어 있는 것을 특징으로 한다.In addition, in order to achieve the other object of the present invention, the semiconductor device mounting PCB may be electrically connected to a copper chip patterned die pattern for mounting a semiconductor chip on a front surface of the PCB and a semiconductor chip mounted on the die pattern. A plurality of lead patterns formed by patterning copper foils to bond wires to be bonded to each other, and the copper foils forming the die patterns and the plurality of lead patterns for electrical connection with external devices during soldering for surface mounting of the device Each of the sides is wrapped to form a solder pattern of a predetermined shape formed by extending to the back portion of the PCB, characterized in that the hole is drilled in a predetermined portion of each pattern.
도 1은 종래 리드프레임을 이용한 반도체소자 제작과정을 순서대로 보이고 있는 공정흐름도,1 is a process flow diagram showing a semiconductor device manufacturing process using a conventional lead frame in order;
도 2는 본 발명에 따른 피씨비의 단면구조를 나타낸 단면도,2 is a cross-sectional view showing a cross-sectional structure of the PCB according to the present invention;
도 3a 및 도 3b는 본 발명에 따른 피씨비의 전면도 및 배면도를 각각 도시한 도면,3a and 3b are respectively a front view and a rear view of the PCB according to the present invention,
도 4는 본 발명의 피씨비 상에 하나의 반도체칩을 탑재하고 와이어를 이용하여 반도체칩과 리드패턴을 연결한 일 실시예의 구조,4 is a structure of an embodiment in which one semiconductor chip is mounted on a PCB of the present invention and a semiconductor chip and a lead pattern are connected using wires;
도 5는 본 발명의 피씨비 상에 두개의 반도체칩을 탑재하고 와이어를 이용하여 두 개의 반도체칩과 복수의 리드패턴을 각각 연결한 다른 실시예의 구조,5 is a structure of another embodiment in which two semiconductor chips are mounted on a PC of the present invention, and two semiconductor chips and a plurality of lead patterns are respectively connected using wires;
도 6은 본 발명의 피씨비 제작과정 및 이 피씨비를 이용하여 반도체칩을 패키징하는 반도체소자 제작과정을 순서대로 보여주고 있는 제작공정 흐름도이다.6 is a manufacturing process flowchart showing the manufacturing process of the present invention and the process of manufacturing a semiconductor device for packaging a semiconductor chip using the PC.
*** 도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
10 : 리드프레임 11 : 다이10: lead frame 11: die
12 : 리드 13,23,43,53,63 : 반도체칩12: lead 13,23,43,53,63: semiconductor chip
14,24,44,54,64 : 와이어 16 : 수지잔류물14,24,44,54,64: Wire 16: Resin residue
17 : 틴 플레이트 21,31,41,51,61 : 다이패턴17: Tin plate 21,31,41,51,61: Die pattern
22,32,42,52,62 : 리드패턴 25 : 측면 동박22,32,42,52,62: Lead pattern 25: Side copper foil
26,36 : 솔더패턴 20,60 : 피씨비26,36: Solder pattern 20,60: PC
65 : 몰드 68 : 도금통로65: mold 68: plating passage
29,39,49,59,69 : 홀29,39,49,59,69: Hall
이하, 첨부도면을 참조하여 본 발명에 따른 반도체소자 및 그 제작방법을 보다 상세히 설명하기로 한다.Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면에서 도 2는 본 발명에 따른 피씨비의 단면구조를 나타낸 단면도, 도 3a 및 도 3b는 본 발명에 따른 피씨비의 전면도 및 배면도를 각각 도시한 도면이고, 도 4는 본 발명의 피씨비 상에 하나의 반도체칩을 탑재하고 와이어를 이용하여 칩과 리드패턴을 연결한 일 실시예의 구조를 나타낸 것이고, 도 5는 본 발명의 피씨비 상에 두개의 반도체칩을 탑재하고 와이어를 이용하여 두 개의 칩과 복수의 리드패턴을 각각 연결한 다른 실시예의 구조를 나타낸 것이며, 도 6은 본 발명의 피씨비 제작과정 및 이 피씨비를 이용하여 반도체칩을 패키징하는 반도체소자 제작과정을 순서대로 보여주고 있는 제작공정 흐름도이다.In the accompanying drawings, Figure 2 is a cross-sectional view showing a cross-sectional structure of the PCB according to the present invention, Figures 3A and 3B are respectively a front view and a rear view of the PCB according to the present invention, Figure 4 is a PCB of the present invention FIG. 5 shows a structure of an embodiment in which one semiconductor chip is mounted on a substrate and a chip and a lead pattern are connected using wires. FIG. 5 shows two semiconductor chips mounted on a PCB of the present invention and two using a wire. 6 shows a structure of another embodiment in which a chip and a plurality of lead patterns are connected to each other, and FIG. 6 illustrates a manufacturing process of a manufacturing process of a PC of the present invention and a process of manufacturing a semiconductor device for packaging a semiconductor chip using the PC. It is a flow chart.
먼저, 본 발명의 피씨비 제작과정을 도 6을 참조하여 살펴보면, 도 6a와 같이 미리 준비된 반도체소자 탑재용 피씨비(60) 상에 액체상태의 동을 이용하여 동박을 형성시킬 때 배면쪽으로 액상의 동이 흘러 소정형태의 동박패턴을 형성시킬 수 있도록 사각형상의 도금통로(68)를 도 6b와 같이 천공하고, 액상의 동을 피씨비 상에 흘려 피씨비의 전면에 동박을 형성함과 동시에 상기 사각형상의 도금통로(68)를 통해 흘러 들어간 액상의 동에 의해 소정형태의 동박을 배면에 형성한 다음, 소정형태의 동박이 형성된 피씨비에 반도체칩을 탑재하여 본딩할 수 있는 형태로 피씨비의 다이패턴(61) 및 리드패턴(62)을 도 6c와 같이 형성하고, 상기 소정형태의 동박이 형성된 피씨비를 반도체칩을 탑재할 수 있는 형태로 피씨비패턴을 도 6c와 같이 형성하고, 도 6d와 같이 상기 피씨비 상의 각 동박패턴 소정부위에 원형의 구멍을 천공하여서 원하는 피씨비를 제작한다.First, referring to Figure 6 of the manufacturing process of the present invention, the liquid copper flows to the rear side when the copper foil is formed using the copper in the liquid state on the PCB 60 for mounting the semiconductor device prepared in advance as shown in Figure 6a To form a copper foil pattern of a predetermined shape, a rectangular plating passage 68 is drilled as shown in FIG. 6B, and liquid copper is flowed on the PCB to form copper foil on the entire surface of the PCB, and at the same time, the rectangular plating passage 68 is formed. The copper foil of the predetermined type is formed on the back by the liquid copper flowing through the sheet), and then the die pattern 61 and the lead pattern of the PCB are formed in such a way that the semiconductor chip can be bonded to the PCB on which the predetermined type of copper foil is formed. 6C is formed as shown in FIG. 6C, and the PCB pattern is formed as shown in FIG. 6C in such a manner that the semiconductor chip can be mounted on the PCB formed with the copper foil of the predetermined shape. A desired hole is produced by drilling a circular hole in a predetermined portion of each copper foil pattern on the piece of PCB.
상기와 같이 제작된 피씨비의 단면구조를 도 2를 참조하여 보면, 피씨비(20)의 전면에 반도체칩(23)을 탑재하기 위하여 동박패터닝된 반도체칩 탑재용 다이패턴(21)과, 상기 다이패턴(21)에 탑재되는 반도체칩(23)을 전기적으로 연결할 수 있도록 와이어(24)를 본딩할 수 있게 동박을 패터닝하여 형성한 복수의 리드패턴(22)을 형성하고, 소자의 표면실장을 위한 솔더링시 외부소자와의 전기적 연결을 위하여 상기 다이패턴(21) 및 복수의 리드패턴(22)을 이루고 있는 동박이 피씨비(20)의 측면을 각각 감싸면서 피씨비의 배면 부위까지 연장되어 이루어진 소정형태의 솔더패턴(36)들이 각각 형성되어 있는 구조로 되어 있으며, 상기 각 패턴(21,22)의 소정부위에 홀(29)이 천공되어 있는 것을 특징으로 한다.Referring to FIG. 2, the cross-sectional structure of the PCB manufactured as described above is shown. The die pattern 21 for mounting a semiconductor chip on the front surface of the PCB 20 and the die pattern 21 for copper chip patterning are mounted. A plurality of lead patterns 22 formed by patterning copper foil to bond the wires 24 so as to electrically connect the semiconductor chips 23 mounted on the 21 may be formed and soldered for surface mounting of the device. To form an electrical connection with an external device, a copper foil forming the die pattern 21 and the plurality of lead patterns 22 is extended to the rear portion of the PCB while covering the sides of the PCB 20, respectively. Each of the patterns 36 is formed, and a hole 29 is formed in a predetermined portion of each of the patterns 21 and 22.
도 3a 및 도 3b는 상기한 구조의 본 발명에 따른 반도체소자 제작을 위해 리드프레임 대신에 사용되는 피씨비의 전면도 및 배면도를 각각 도시한 도면이며, 도 2와 동일한 부분에 대해서는 부호의 끝자리를 동일한 숫자로 표시하고 그 설명은 생략하였다.3A and 3B illustrate front and rear views of PCs used in place of a lead frame for fabricating a semiconductor device having the above-described structure, respectively. The same numerals are used and the description is omitted.
이와 같이 형성된 본 발명의 피씨비 상에 한개의 반도체칩을 탑재하고 와이어를 이용하여 다이패턴에 탑재된 반도체칩과 리드패턴을 연결한 일 실시예의 구조가 도 4에 도시되어 있으며, 또, 상기한 구조의 본 발명의 피씨비 다이 상에 두개의 반도체칩을 각각 탑재하고 와이어를 이용하여 두 개의 반도체칩과 복수의 리드패턴을 각각 연결시킴으로써 한개의 반도체소자에 두 개의 반도체칩이 내장된 다른 실시예의 구조가 도 5에 도시되어 있다. 여기에서도 도 3의 설명에서와 마찬가지로 본 발명의 도면들에 있어서 동일부분은 부호의 끝자리를 동일한 숫자로 표시하면서 그 설명은 생략하기로 한다.The structure of an embodiment in which one semiconductor chip is mounted on the PCB of the present invention formed as described above, and the semiconductor chip mounted on the die pattern and the lead pattern are connected to each other is shown in FIG. 4. According to the embodiment of the present invention, two semiconductor chips are mounted on the PCB die of the present invention, and two semiconductor chips and a plurality of lead patterns are connected to each other using wires. 5 is shown. Here, as in the description of FIG. 3, in the drawings of the present invention, the same parts are denoted by the same numerals and the description thereof will be omitted.
도 6은 본 발명의 피씨비 제작과정 및 이 피씨비를 이용하여 반도체칩을 패키징하는 반도체소자 제작과정을 순서대로 보여주고 있는 제작공정 흐름도로서, 이 도면을 참조하여 본 발명에 따른 피씨비 제작과정 및 피씨비 상에 반도체칩을 탑재하여 패키징하는 반도체소자 전제작과정을 설명하면 다음과 같다.6 is a manufacturing process flow chart showing the manufacturing process of the present invention of the present invention and the semiconductor device for packaging the semiconductor chip using the PC in order, referring to the present invention with reference to this figure The prefabrication process of the semiconductor device packaged with the semiconductor chip is as follows.
먼저, 상술한 바와 같이 준비된 반도체칩 탑재용 피씨비(60)(도 6a) 상에 액체상태의 동을 이용하여 다이패턴(61) 및 복수의 리드패턴(62)용 동박을 형성시킬 때 배면쪽으로 액상의 동이 흘러 소정형태의 솔더패턴용 동박이 형성될 수 있도록 사각형상의 도금통로(68)를 천공하여(도 6b), 액상의 동을 피씨비 상에 흘려 피씨비의 전면에 다이패턴(61) 및 복수의 리드패턴(62)을 형성함과 동시에 상기 사각형상의 도금통로를 통해 흘러 들어간 액상의 동에 의해 소정형태의 솔더패턴(도 6에는 도시되지 않음)을 배면에 각각 형성한 다음, 상기 소정형태의 동박이 형성된 피씨비를 반도체칩(63)을 탑재할 수 있는 형태로 피씨비의 패턴을 형성하고(도 6c), 상기 피씨비 상의 각 동박패턴 소정부위에 원형의 구멍을 천공하여서(도 6d ) 원하는 반도체소자 탑재용 피씨비가 제작된다.First, when the copper foils for the die pattern 61 and the plurality of lead patterns 62 are formed using copper in a liquid state on the semiconductor chip mounting PCB 60 (FIG. 6A) prepared as described above, In order to form a copper foil for a solder pattern of a predetermined shape, a rectangular plating passage 68 is drilled (FIG. 6B), and liquid copper is flowed on the PCB so that the die pattern 61 and the plurality of dies are formed on the front of the PCB. The solder pattern (not shown in FIG. 6) is formed on the back by the liquid copper flowing through the rectangular plating passage at the same time as the lead pattern 62 is formed, and then the copper foil of the predetermined form is formed. The formed PCB is formed in such a manner that the semiconductor chip 63 can be mounted thereon (Fig. 6C), and a desired hole is mounted by drilling a circular hole in a predetermined portion of each copper foil pattern on the PCB (Fig. 6D). Dragon Is produced.
상기와 같은 과정을 통해 제작된 반도체칩 탑재용 피씨비 상에 도 6e와 같이 피씨비 다이패턴(61) 위에 반도체칩(63)를 다이본딩하고, 이어서 다이본딩된 반도체칩(63)의 본딩패드(도시되지 않음)와 다이패턴(61)의 양측에 형성된 복수의 리드패턴(62)을 와이어(64)를 이용해서 선택적으로 와이어본딩한 다음(도 6f), 수지를 이용하여 상기 반도체칩이 탑재된 다이패턴(61) 및 리드패턴(62)을 포함한 피씨비의 소정부위를 일정한 크기로 몰딩하여 반도체소자를 패키징하고(도 6g), 소잉(sawing)하여 각 반도체소자를 분리시킴으로서 반도체소자의 제작이 완료되어 진다(도 6h).The semiconductor chip 63 is bonded onto the PCB die pattern 61 as shown in FIG. 6E on the semiconductor chip mounting PCB manufactured through the above process, and then a bonding pad (shown) of the die-bonded semiconductor chip 63 is illustrated. And a plurality of lead patterns 62 formed on both sides of the die pattern 61 are selectively wire-bonded using the wire 64 (FIG. 6F), and then the die on which the semiconductor chip is mounted using resin. The manufacturing of the semiconductor device is completed by molding a predetermined portion of the PCB including the pattern 61 and the lead pattern 62 into a predetermined size to package the semiconductor devices (FIG. 6G), sawing and separating each semiconductor device. (FIG. 6H).
상술한 바와 같이, 본 발명에 따르면, 종래 수지몰딩과정에서 패키지의 외측에 수지잔류물의 잔재로 행하는 세척공정과 외측에 노출되는 리드프레임의 틴 플레이팅공정을 생략할 수 있으므로 제조공정속도를 향상시킴은 물론 원자재가격 절감을 통해 제작비용을 절감하여 제품가격을 절하할 수 있는 효과가 있는 것이다.As described above, according to the present invention, it is possible to omit the washing process performed with the residue of the resin residue on the outside of the package and the tin plating process of the lead frame exposed to the outside in the conventional resin molding process, thereby improving the manufacturing process speed. Of course, it is possible to reduce the product price by reducing the production cost through raw material price reduction.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980017694A KR100325242B1 (en) | 1998-05-15 | 1998-05-15 | Semiconductor device and fabricating method thereof |
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| KR1019980017694A KR100325242B1 (en) | 1998-05-15 | 1998-05-15 | Semiconductor device and fabricating method thereof |
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| KR100325242B1 true KR100325242B1 (en) | 2002-04-17 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61287128A (en) * | 1985-06-13 | 1986-12-17 | Matsushita Electric Works Ltd | Chip carrier for electron element |
| JPH03171760A (en) * | 1989-11-30 | 1991-07-25 | Oki Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPH06112364A (en) * | 1992-09-24 | 1994-04-22 | Sumitomo Bakelite Co Ltd | Semiconductor mounter |
| JPH07106485A (en) * | 1993-09-29 | 1995-04-21 | Citizen Watch Co Ltd | Resin-sealed pin grid array |
| JPH07193166A (en) * | 1993-11-19 | 1995-07-28 | Citizen Watch Co Ltd | Semiconductor device with solder bump and manufacture thereof |
-
1998
- 1998-05-15 KR KR1019980017694A patent/KR100325242B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61287128A (en) * | 1985-06-13 | 1986-12-17 | Matsushita Electric Works Ltd | Chip carrier for electron element |
| JPH03171760A (en) * | 1989-11-30 | 1991-07-25 | Oki Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPH06112364A (en) * | 1992-09-24 | 1994-04-22 | Sumitomo Bakelite Co Ltd | Semiconductor mounter |
| JPH07106485A (en) * | 1993-09-29 | 1995-04-21 | Citizen Watch Co Ltd | Resin-sealed pin grid array |
| JPH07193166A (en) * | 1993-11-19 | 1995-07-28 | Citizen Watch Co Ltd | Semiconductor device with solder bump and manufacture thereof |
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